1. 24 Feb, 2016 1 commit
    • Marek Vasut's avatar
      arm: socfpga: Fix ethernet reset handling · e6e34ca3
      Marek Vasut authored
      The following patch caused cpu_eth_init() to not be called anymore
      for DM-capable boards:
      
      commit c32a6fd0
      Date:   Sun Jan 17 14:51:56 2016 -0700
          net: Don't call board/cpu_eth_init() with driver model
      
      This breaks ethernet on SoCFPGA, since we use that function to un-reset
      the ethernet blocks. Invoke the ethernet reset function from arch_misc_init()
      instead to fix the breakage.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
      e6e34ca3
  2. 22 Dec, 2015 2 commits
  3. 06 Dec, 2015 1 commit
    • Marek Vasut's avatar
      arm: socfpga: Remove cpu_mmc_init() · 1c75596e
      Marek Vasut authored
      This function triggers the registration of the dwmmc driver on SoCFPGA,
      but this is not needed in case the driver is correctly probed from DT.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Tom Rini <trini@konsulko.com>
      1c75596e
  4. 16 Oct, 2015 1 commit
    • Dinh Nguyen's avatar
      arm: socfpga: enable data/inst prefetch and shared override in the L2 · 8d8e13e1
      Dinh Nguyen authored
      Update the L2 AUX CTRL settings for the SoCFPGA.
      
      Enabling D and I prefetch bits helps improve SDRAM performance on the
      platform.
      
      Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
      PL310 Auxiliary Control register (shared attribute override enable) has the
      side effect of transforming Normal Shared Non-cacheable reads into Cacheable
      no-allocate reads.
      
      Coherent DMA buffers in Linux always have a Cacheable alias via the
      kernel linear mapping and the processor can speculatively load cache
      lines into the PL310 controller. With bit 22 cleared, Non-cacheable
      reads would unexpectedly hit such cache lines leading to buffer
      corruption.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      8d8e13e1
  5. 04 Sep, 2015 1 commit
    • Marek Vasut's avatar
      mmc: dw_mmc: Probe the MMC from OF · 129adf5b
      Marek Vasut authored
      Rework the driver to probe the MMC controller from Device Tree
      and make it mandatory. There is no longer support for probing
      from the ancient qts-generated header files.
      
      This patch now also removes previous temporary workaround.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
      Cc: Tom Rini <trini@konsulko.com>
      129adf5b
  6. 08 Aug, 2015 8 commits
  7. 07 May, 2015 1 commit
  8. 18 Apr, 2015 1 commit
  9. 21 Dec, 2014 1 commit
    • Stefan Roese's avatar
      arm: socfpga: Change watchdog timeout · d0e932de
      Stefan Roese authored
      The current current watchdog timeout of 12 seconds is a bit small for
      booting into Linux, especially when using a NFS based rootfs. So lets
      change this timeout to a more defensive value of 30 seconds.
      
      Also we now call the hw_watchdog_init() function so that we override
      the value already configured from the Preloader.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Vince Bridgers <vbridger@opensource.altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      d0e932de
  10. 07 Nov, 2014 1 commit
    • Stefan Roese's avatar
      arm: socfpga: Add socfpga_spim_enable() to reset_manager.c · a877bec3
      Stefan Roese authored
      This function will be needed by the upcoming Designware master SPI
      driver. As the SPI master controller is held in reset by the current
      Preloader implementation. So we need to release the reset for the
      driver to communicate with the controller.
      
      This function is called from arch_early_init_r() if the SPI
      driver is enabled.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      a877bec3
  11. 27 Oct, 2014 1 commit
  12. 06 Oct, 2014 9 commits
    • Marek Vasut's avatar
      arm: socfpga: Add command to control HPS-FPGA bridges · 7249fafb
      Marek Vasut authored
      Add command to enable and disable the bridges between HPS and FPGA.
      
      This patch does have a checkpatch issue with the assembler portion,
      checkpatch correctly complains that there should be no whitespace
      before quoted newline. I do not agree that fixing this specific
      checkpatch issue will improve the readability, thus this one is not
      addressed.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Wolfgang Denk <wd@denx.de>
      7249fafb
    • Marek Vasut's avatar
      arm: socfpga: Move cache_enable to CPU code · 4ab333b7
      Marek Vasut authored
      Move icache_enable() and dcache_enable() function calls from
      board code into the CPU code and into the enable_caches()
      function. This is how the cache enabling code was designed
      to work.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      4ab333b7
    • Pavel Machek's avatar
      arm: socfpga: nic301: Add NIC-301 configuration code · 13e81d45
      Pavel Machek authored
      Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
      The code sets the access permissions for the CPU to the AMBA slaves such
      that the CPU can access them in both secure and non-secure mode.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      13e81d45
    • Marek Vasut's avatar
      arm: socfpga: pl310: Map SDRAM to 0x0 · 60d804c2
      Marek Vasut authored
      Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
      This code also configures the "remap" register of NIC-301 and sets the
      required 'mpuzero' bit.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      60d804c2
    • Pavel Machek's avatar
      arm: socfpga: fpga: Add SoCFPGA FPGA programming interface · 230fe9b2
      Pavel Machek authored
      Add code necessary to program the FPGA part of SoCFPGA from U-Boot
      with an RBF blob. This patch also integrates the code into the
      FPGA driver framework in U-Boot so it can be used via the 'fpga'
      command.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      
      V2: Move the not-CPU specific stuff into drivers/fpga/ and base
          this on the cleaned up altera FPGA support.
      230fe9b2
    • Pavel Machek's avatar
      arm: socfpga: misc: Align print_cpuinfo() output · d5a3d3c9
      Pavel Machek authored
      Cosmetic change to the print_cpuinfo() function output. Align the
      output with the rest of initial output produced by U-Boot.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      d5a3d3c9
    • Pavel Machek's avatar
      arm: socfpga: misc: Add SD controller init · 4e736869
      Pavel Machek authored
      Add CPU function to register and initialize the dw_mmc SD controller.
      This allows us to use the HPS SDMMC block.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      4e736869
    • Pavel Machek's avatar
      arm: socfpga: misc: Add proper ethernet initialization · 45d6e677
      Pavel Machek authored
      Add function to initialize the EMAC blocks upon board startup.
      The preprocessor guards against building on SoCFPGA-VT and against
      SPL build are not needed as those are handled implicitly via both
      SPL framework and the socfpga_cyclone5.h config file, which will
      not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.
      
      We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
      Once there is hardware using both EMAC blocks, this ifdef will have
      to go.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      45d6e677
    • Pavel Machek's avatar
      arm: socfpga: Add watchdog disable for socfpga · de6da925
      Pavel Machek authored
      This adds watchdog disable. It is neccessary for running Linux kernel.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      
      V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
          Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
      de6da925
  13. 30 Aug, 2014 1 commit
  14. 05 Jul, 2014 1 commit
  15. 06 Sep, 2013 1 commit
  16. 24 Jul, 2013 1 commit
  17. 04 Oct, 2012 1 commit