1. 09 Feb, 2017 1 commit
  2. 07 Feb, 2017 2 commits
  3. 26 Nov, 2016 4 commits
  4. 17 Mar, 2016 2 commits
  5. 24 Jan, 2016 1 commit
  6. 13 Jan, 2016 1 commit
  7. 09 Dec, 2015 3 commits
  8. 03 Sep, 2015 1 commit
  9. 15 Jul, 2015 1 commit
  10. 12 May, 2015 1 commit
  11. 30 Apr, 2015 2 commits
  12. 18 Apr, 2015 2 commits
  13. 17 Apr, 2015 1 commit
    • Simon Glass's avatar
      x86: Add support for panther (Asus Chromebox) · 51e9dad2
      Simon Glass authored
      Support running U-Boot as a coreboot payload. Tested peripherals include:
      - Video (HDMI and DisplayPort)
      - SATA disk
      - Gigabit Ethernet
      - SPI flash
      USB3 does not work. This may be a problem with the USB3 PCI driver or
      something in the USB3 stack and has not been investigated So far this is
      disabled. The SD card slot also does not work.
      For video, coreboot will need to run the OPROM to set this up.
      With this board, bare support (running without coreboot) is not available
      as yet.
      Signed-off-by: 's avatarSimon Glass <sjg@chromium.org>
  14. 06 Feb, 2015 1 commit
  15. 13 Jan, 2015 2 commits
  16. 19 Dec, 2014 1 commit
  17. 14 Dec, 2014 2 commits
  18. 25 Nov, 2014 2 commits
  19. 21 Nov, 2014 4 commits
    • Simon Glass's avatar
      x86: chromebook_link: Enable GPIO support · 437c2b7c
      Simon Glass authored
      Enable GPIO support and provide the required GPIO setup information to
      the driver.
      Signed-off-by: 's avatarSimon Glass <sjg@chromium.org>
    • Simon Glass's avatar
      x86: chromebook_link: Implement CAR support (cache as RAM) · 70a09c6c
      Simon Glass authored
      Add support for CAR so that we have memory to use prior to DRAM init.
      On link there is a total of 128KB of CAR available, although some is
      used for the memory reference code.
      Signed-off-by: 's avatarSimon Glass <sjg@chromium.org>
    • Simon Glass's avatar
      x86: Emit post codes in startup code for Chromebooks · d1cd0459
      Simon Glass authored
      On x86 it is common to use 'post codes' which are 8-bit hex values emitted
      from the code and visible to the user. Traditionally two 7-segment displays
      were made available on the motherboard to show the last post code that was
      emitted. This allows diagnosis of a boot problem since it is possible to
      see where the code got to before it died.
      On modern hardware these codes are not normally visible. On Chromebooks
      they are displayed by the Embedded Controller (EC), so it is useful to emit
      them. We must enable this feature for the EC to see the codes, so add an
      option for this.
      Signed-off-by: 's avatarSimon Glass <sjg@chromium.org>
      Reviewed-by: 's avatarBin Meng <bmeng.cn@gmail.com>
    • Simon Glass's avatar
      x86: Add chromebook_link board · 8ef07571
      Simon Glass authored
      This board is a 'bare' version of the existing 'link 'board. It does not
      require coreboot to run, but is intended to start directly from the reset
      This initial commit has place holders for a wide range of features. These
      will be added in follow-on patches and series. So far it cannot be booted
      as there is no ROM image produced, but it does build without errors.
      Signed-off-by: 's avatarSimon Glass <sjg@chromium.org>