1. 25 Aug, 2016 1 commit
    • Stephen Warren's avatar
      spi: tegra: fix hang in set_mode() · 4832c7f5
      Stephen Warren authored
      In tegra20_slink.c, the set_mode() function may be executed before the
      SPI bus is claimed the first time, and hence the clocks to the SPI
      controller may not be running. If so, any register read/write at this
      time will hang the CPU. Fix this by ensuring the clock is running as soon
      as the driver is probed. This is observed on the Tegra30 Beaver board.
      
      Apply the same clock initialization fix to all other Tegra SPI drivers so
      that if set_mode() is ever implemented there, the same bug will not appear.
      Note that tegra114_spi.c already operates in this fashion.
      
      The clock manipulation code is copied from claim_bus() to probe() rather
      than moved. This ensures that any calls to set_speed() take effect; the
      clock can't be set once during probe and left unchanged.
      
      Fixes: 5cb1b7b3 ("spi: tegra20: Add support for mode selection")
      Cc: Mirza Krak <mirza.krak@hostmobility.com>
      Signed-off-by: 's avatarStephen Warren <swarren@nvidia.com>
      Reviewed-by: 's avatarSimon Glass <sjg@chromium.org>
      Signed-off-by: 's avatarTom Warren <twarren@nvidia.com>
      4832c7f5
  2. 07 Aug, 2016 1 commit
    • Chin Liang See's avatar
      spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value · 5405817a
      Chin Liang See authored
      Ensuring the baudrate divisor value doesn't exceed the max value
      in the calculation.It will be capped at max value to ensure the
      correct value being written into the register.
      
      Example of the existing bug is when calculated div = 16. After and
      with the mask, the value written to register is actually 0 (register
      field for baudrate divisor). With this fix, the value written is now
      15 which is max value for baudrate divisor.
      Signed-off-by: 's avatarChin Liang See <clsee@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Jagan Teki <jteki@openedev.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      5405817a
  3. 02 Aug, 2016 1 commit
  4. 29 Jul, 2016 4 commits
  5. 27 Jul, 2016 2 commits
  6. 09 Jul, 2016 4 commits
  7. 06 Jul, 2016 1 commit
  8. 01 Jul, 2016 1 commit
  9. 19 Jun, 2016 1 commit
    • Stephen Warren's avatar
      clk: convert API to match reset/mailbox style · 135aa950
      Stephen Warren authored
      The following changes are made to the clock API:
      * The concept of "clocks" and "peripheral clocks" are unified; each clock
        provider now implements a single set of clocks. This provides a simpler
        conceptual interface to clients, and better aligns with device tree
        clock bindings.
      * Clocks are now identified with a single "struct clk", rather than
        requiring clients to store the clock provider device and clock identity
        values separately. For simple clock consumers, this isolates clients
        from internal details of the clock API.
      * clk.h is split so it only contains the client/consumer API, whereas
        clk-uclass.h contains the provider API. This aligns with the recently
        added reset and mailbox APIs.
      * clk_ops .of_xlate(), .request(), and .free() are added so providers
        can customize these operations if needed. This also aligns with the
        recently added reset and mailbox APIs.
      * clk_disable() is added.
      * All users of the current clock APIs are updated.
      * Sandbox clock tests are updated to exercise clock lookup via DT, and
        clock enable/disable.
      * rkclk_get_clk() is removed and replaced with standard APIs.
      
      Buildman shows no clock-related errors for any board for which buildman
      can download a toolchain.
      
      test/py passes for sandbox (which invokes the dm clk test amongst
      others).
      Signed-off-by: 's avatarStephen Warren <swarren@nvidia.com>
      Acked-by: 's avatarSimon Glass <sjg@chromium.org>
      135aa950
  10. 10 Jun, 2016 1 commit
  11. 23 May, 2016 1 commit
    • Martin Hejnfelt's avatar
      omap3: Fix SPI registers on am33xx and am43xx · 5f89a15e
      Martin Hejnfelt authored
      When the base registers are read from device tree the base is not
      0x48030100 as the driver expects, but 0x48030000, resulting in
      non functioning SPI. To deal with this, use same idea as how this
      is done in the linux kernel (drivers/spi/spi-omap2-mcspi.c) and
      add a structure with a field that is used to shift the registers
      on these systems.
      
      v2: Fixed commit subject line to correct cpu
      Signed-off-by: 's avatarMartin Hejnfelt <mh@newtec.dk>
      5f89a15e
  12. 20 May, 2016 2 commits
  13. 18 May, 2016 3 commits
  14. 17 May, 2016 3 commits
  15. 06 May, 2016 2 commits
    • Marek Vasut's avatar
      mtd: cqspi: Simplify indirect read code · 5a824c49
      Marek Vasut authored
      The indirect read code is a pile of nastiness. This patch replaces
      the whole unmaintainable indirect read implementation with the one
      from upcoming Linux CQSPI driver, which went through multiple rounds
      of thorough review and testing. All the patch does is it plucks out
      duplicate ad-hoc code distributed across the driver and replaces it
      with more compact code doing exactly the same thing. There is no
      speed change of the read operation.
      Signed-off-by: 's avatarMarek Vasut <marex@denx.de>
      Cc: Anatolij Gustschin <agust@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Jagan Teki <jteki@openedev.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Vignesh R <vigneshr@ti.com>
      5a824c49
    • Marek Vasut's avatar
      mtd: cqspi: Simplify indirect write code · 26da6353
      Marek Vasut authored
      The indirect write code is buggy pile of nastiness which fails horribly
      when the system runs fast enough to saturate the controller. The failure
      results in some pages (256B) not being written to the flash. This can be
      observed on systems which run with Dcache enabled and L2 cache enabled,
      like the Altera SoCFPGA.
      
      This patch replaces the whole unmaintainable indirect write implementation
      with the one from upcoming Linux CQSPI driver, which went through multiple
      rounds of thorough review and testing. While this makes the patch look
      terrifying and violates all best-practices of software development, all
      the patch does is it plucks out duplicate ad-hoc code distributed across
      the driver and replaces it with more compact code doing exactly the same
      thing.
      Signed-off-by: 's avatarMarek Vasut <marex@denx.de>
      Cc: Anatolij Gustschin <agust@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Jagan Teki <jteki@openedev.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Vignesh R <vigneshr@ti.com>
      26da6353
  16. 06 Apr, 2016 1 commit
  17. 04 Apr, 2016 1 commit
  18. 15 Mar, 2016 1 commit
  19. 14 Mar, 2016 3 commits
  20. 12 Mar, 2016 1 commit
  21. 23 Feb, 2016 3 commits
  22. 05 Feb, 2016 2 commits