1. 07 Aug, 2016 1 commit
    • Chin Liang See's avatar
      spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value · 5405817a
      Chin Liang See authored
      Ensuring the baudrate divisor value doesn't exceed the max value
      in the calculation.It will be capped at max value to ensure the
      correct value being written into the register.
      
      Example of the existing bug is when calculated div = 16. After and
      with the mask, the value written to register is actually 0 (register
      field for baudrate divisor). With this fix, the value written is now
      15 which is max value for baudrate divisor.
      Signed-off-by: default avatarChin Liang See <clsee@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Jagan Teki <jteki@openedev.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      5405817a
  2. 09 Jul, 2016 2 commits
  3. 06 May, 2016 2 commits
    • Marek Vasut's avatar
      mtd: cqspi: Simplify indirect read code · 5a824c49
      Marek Vasut authored
      The indirect read code is a pile of nastiness. This patch replaces
      the whole unmaintainable indirect read implementation with the one
      from upcoming Linux CQSPI driver, which went through multiple rounds
      of thorough review and testing. All the patch does is it plucks out
      duplicate ad-hoc code distributed across the driver and replaces it
      with more compact code doing exactly the same thing. There is no
      speed change of the read operation.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Anatolij Gustschin <agust@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Jagan Teki <jteki@openedev.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Vignesh R <vigneshr@ti.com>
      5a824c49
    • Marek Vasut's avatar
      mtd: cqspi: Simplify indirect write code · 26da6353
      Marek Vasut authored
      The indirect write code is buggy pile of nastiness which fails horribly
      when the system runs fast enough to saturate the controller. The failure
      results in some pages (256B) not being written to the flash. This can be
      observed on systems which run with Dcache enabled and L2 cache enabled,
      like the Altera SoCFPGA.
      
      This patch replaces the whole unmaintainable indirect write implementation
      with the one from upcoming Linux CQSPI driver, which went through multiple
      rounds of thorough review and testing. While this makes the patch look
      terrifying and violates all best-practices of software development, all
      the patch does is it plucks out duplicate ad-hoc code distributed across
      the driver and replaces it with more compact code doing exactly the same
      thing.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Anatolij Gustschin <agust@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Jagan Teki <jteki@openedev.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Vignesh R <vigneshr@ti.com>
      26da6353
  4. 27 Oct, 2015 1 commit
  5. 03 Jul, 2015 3 commits
  6. 06 Dec, 2014 1 commit
    • Stefan Roese's avatar
      spi: Add Cadence QSPI DM driver used by SoCFPGA · 10e8bf88
      Stefan Roese authored
      This driver is cloned from the Altera Rockerboard.org U-Boot
      repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
      modification to support the U-Boot driver model (DM).
      
      As mentioned above, in this new version I ported this driver to the
      new driver model (DM). One big advantage of this move is that now
      multiple SPI drivers can be enabled on one platform. And since the
      SoCFPGA also has the Designware SPI master controller integrated,
      this feature is really needed to support both controllers.
      
      Because of this, this series needs the DT support for SoCFPGA
      to be applied. For DT based probing in the SPI DM.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
      10e8bf88