1. 17 May, 2016 3 commits
  2. 21 Mar, 2016 1 commit
  3. 25 Jan, 2016 1 commit
  4. 19 Jan, 2016 1 commit
  5. 14 Dec, 2015 1 commit
  6. 30 Oct, 2015 1 commit
  7. 23 Apr, 2015 2 commits
  8. 11 Dec, 2014 1 commit
  9. 25 Sep, 2014 2 commits
  10. 08 Sep, 2014 1 commit
  11. 23 Apr, 2014 2 commits
  12. 21 Feb, 2014 1 commit
  13. 25 Nov, 2013 1 commit
  14. 16 Oct, 2013 1 commit
  15. 09 Aug, 2013 2 commits
  16. 22 Oct, 2012 3 commits
    • York Sun's avatar
      powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT · f31cfd19
      York Sun authored
      When ECC is enabled, DDR controller needs to initialize the data and ecc.
      The wait time can be calcuated with total memory size, bus width, bus speed
      and interleaving mode. If it went wrong, it is bettert to timeout than
      waiting for D_INIT to clear, where it probably hangs.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
    • York Sun's avatar
      powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation · 123922b1
      York Sun authored
      Fix handling quad-rank DIMMs in a system with two DIMM slots and first
      slot supports both dual-rank DIMM and quad-rank DIMM.
      For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
      registers need to be enabled to maintain proper ODT operation. The
      inactive CS should have bnds registers cleared.
      Fix the turnaround timing for systems with all chip-selects enabled. This
      wasn't an issue before because DDR was running lower than 1600MT/s with
      this interleaving mode.
      Fix DDR address calculation. It wasn't an issue until we have multiple
      controllers with each more than 4GB and interleaving is disabled.
      It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
      when debugging DDR and first DDR controller is disabled. With the fix,
      the first enabled controller information will be displayed.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
    • York Sun's avatar
      powerpc/mpc8xxx: Update DDR registers · 57495e4e
      York Sun authored
      DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
      set for speed lower than 1250MT/s.
      CDR1 and CDR2 are control driver registers. ODT termination valueis for
      IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
      	000 -> Termsel off
      	001 -> 120 Ohm
      	010 -> 180 Ohm
      	011 -> 75 Ohm
      	100 -> 110 Ohm
      	101 -> 60 Ohm
      	110 -> 70 Ohm
      	111 -> 47 Ohm
      Add two write leveling registers. Each QDS now has its own write leveling
      start value. In case of zero value, the value of QDS0 will be used. These
      values are board-specific and are set in board files.
      Extend DDR register timing_cfg_1 to have 4 bits for each field.
      DDR control driver registers and write leveling registers are added to
      interactive debugging for easy access.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
  17. 23 Aug, 2012 2 commits
  18. 30 Sep, 2011 2 commits
  19. 11 Jul, 2011 2 commits
  20. 05 Apr, 2011 1 commit
  21. 04 Apr, 2011 2 commits
  22. 03 Feb, 2011 1 commit
  23. 20 Jan, 2011 4 commits
  24. 14 Jan, 2011 2 commits
    • Kumar Gala's avatar
      powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code · 3dbd5d7d
      Kumar Gala authored
      Move the parsing of hwconfig to determine if to use spd into common code
      so we can share it across all boards instead of duplicating it
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Becky Bruce's avatar
      mpc85xx boards: initdram() cleanup/bugfix · 38dba0c2
      Becky Bruce authored
      Correct initdram to use phys_size_t to represent the size of
      dram; instead of changing this all over the place, and correcting
      all the other random errors I've noticed, create a
      common initdram that is used by all non-corenet 85xx parts.  Most
      of the initdram() functions were identical, with 2 common differences:
      1) DDR tlbs for the fixed_sdram case were set up in initdram() on
      some boards, and were part of the tlb_table on others.  I have
      changed them all over to the initdram() method - we shouldn't
      be accessing dram before this point so they don't need to be
      done sooner, and this seems cleaner.
      2) Parts that require the DDR11 erratum workaround had different
      implementations - I have adopted the version from the Freescale
      errata document.  It also looks like some of the versions were
      buggy, and, depending on timing, could have resulted in the
      DDR controller being disabled.  This seems bad.
      The xpedite boards had a common/fsl_8xxx_ddr.c; with this
      change only the 517 board uses this so I have moved the ddr code
      into that board's directory in xpedite517x.c
      Signed-off-by: default avatarBecky Bruce <beckyb@kernel.crashing.org>
      Tested-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>