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    • York Sun's avatar
      powerpc/b4860qds: Added Support for B4860QDS · b5b06fb7
      York Sun authored
      B4860QDS is a high-performance computing evaluation, development and
      test platform supporting the B4860 QorIQ Power Architecture processor.
      
      B4860QDS Overview
      ------------------
      - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
        ECC, 4 GB of memory in two ranks of 2 GB.
      - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,  ECC, 2 GB of memory. Single rank.
      - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
        16x16 switch VSC3316
      - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
        8x8 switch VSC3308
      - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
      - B4860 UART port is available over USB-to-UART translator USB2SER or over
        RS232 flat cable.
      - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
        connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
        connector ports 0 and 2 for AMC mode.
      - The B4860 configuration may be loaded from nine bits coded reset
        configuration reset source. The RCW source is set by appropriate
        DIP-switches:
      - 16-bit NOR Flash / PROMJet
      - QIXIS 8-bit NOR Flash Emulator
      - 8-bit NAND Flash
      - 24-bit SPI Flash
      - Long address I2C EEPROM
      - Available debug interfaces are:
      	- On-board eCWTAP controller with ETH and USB I/F
      	- JTAG/COP 16-pin header for any external TAP controller
      	- External JTAG source over AMC to support B2B configuration
      	- 70-pin Aurora debug connector
      - QIXIS (FPGA) logic:
      	- 2 KB internal memory space including
      - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
        DDRCLK1, 2 and RTCCLK.
      - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
        - total four refclk, including CPRI clock scheme
      Signed-off-by: 's avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: 's avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: 's avatarShaveta Leekha <shaveta@freescale.com>
      Signed-off-by: 's avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      Signed-off-by: 's avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: 's avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: 's avatarSandeep Singh <Sandeep@freescale.com>
      Signed-off-by: 's avatarAndy Fleming <afleming@freescale.com>
      b5b06fb7