• Scott Wood's avatar
    powerpc/fsl-corenet: work around erratum A004510 · 33eee330
    Scott Wood authored
    Erratum A004510 says that under certain load conditions, modified
    cache lines can be discarded, causing data corruption.
    
    To work around this, several CCSR and DCSR register updates need to be
    made in a careful manner, so that there is no other transaction in
    corenet when the update is made.
    
    The update is made from a locked cacheline, with a delay before to flush
    any previous activity, and a delay after to flush the CCSR/DCSR update.
    We can't use a readback because that would be another corenet
    transaction, which is not allowed.
    
    We lock the subsequent cacheline to prevent it from being fetched while
    we're executing the previous cacheline.  It is filled with nops so that a
    branch doesn't cause us to fetch another cacheline.
    
    Ordinarily we are running in a cache-inhibited mapping at this point, so
    we temporarily change that.  We make it guarded so that we should never
    see a speculative load, and we never do an explicit load.  Thus, only the
    I-cache should ever fill from this mapping, and we flush/unlock it
    afterward.  Thus we should avoid problems from any potential cache
    aliasing between inhibited and non-inhibited mappings.
    
    NOTE that if PAMU is used with this patch, it will need to use a
    dedicated LAW as described in the erratum.  This is the responsibility
    of the OS that sets up PAMU.
    Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
    Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
    33eee330
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