• Paul Gortmaker's avatar
    sbc8548: Fix LBC SDRAM initialization settings · 5f4c6f0d
    Paul Gortmaker authored
    These were cloned from the mpc8548cds platform which has
    a different memory layout (1/2 the size).  Set the values
    by comparing to the register file for the board used during
    JTAG init sequence:
    
    	LSDMR1		0x2863B727	/* PCHALL */
    	LSDMR2		0x0863B727	/* NORMAL */
    	LSDMR3		0x1863B727	/* MRW    */
    	LSDMR4		0x4063B727	/* RFEN   */
    
    This differs from what was there already in that the RFEN is
    not bundled in all four steps implicitly, but issued once
    as the final step.
    
    The other difference seen when comparing vs. the register file init,
    is that since the memory is split across /CS3 and /CS4, the dummy
    writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
    
    We also rewrite the final LBC SDRAM inits as macros, as there is
    no real need for them to be a local variable that is modified
    on the fly at runtime.
    Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
    Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    5f4c6f0d
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