• Eric Nelson's avatar
    mx6: ddr: pass mx6_ddr_sysinfo to calibration routines · 7f17fb74
    Eric Nelson authored
    The DDR calibration routines have scattered support for bus
    widths other than 64-bits:
    
    -- The mmdc_do_write_level_calibration() routine assumes the
    presence of PHY1, and
    -- The mmdc_do_dqs_calibration() routine tries to determine
    whether one or two DDR PHYs are active by reading MDCTL.
    
    Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
    for use in calling mx6_dram_cfg(), and the bus width is available in the
    "dsize" field, use this structure to inform the calibration routines which
    PHYs are active.
    
    This allows the use of the DDR calibration routines on CPU variants
    like i.MX6SL that only have a single MMDC port.
    Signed-off-by: 's avatarEric Nelson <eric@nelint.com>
    Reviewed-by: 's avatarMarek Vasut <marex@denx.de>
    7f17fb74
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