• Nishanth Menon's avatar
    ARM: keystone2: Add missing privilege ID settings · 2283284b
    Nishanth Menon authored
    Add missing Privilege ID settings for KS2 SoCs.
    
    Based on:
    K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
      http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
    K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
      http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
    K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
      http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
    K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
      http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
    
    Overall mapping:
    -------+-----------+-----------+-----------+---------
    PrivID | KS2H/K    | K2L       | K2E       | K2G
    -------+-----------+-----------+-----------+---------
    0      | C66x 0    | C66x 0    | C66x 0    | C66x 0
    1      | C66x 1    | C66x 1    | Reserved  | ARM
    2      | C66x 2    | C66x 2    | Reserved  | ICSS0
    3      | C66x 3    | C66x 3    | Reserved  | ICSS1
    4      | C66x 4    | Reserved  | Reserved  | NETCP
    5      | C66x 5    | Reserved  | Reserved  | CPIE
    6      | C66x 6    | Reserved  | Reserved  | USB
    7      | C66x 7    | Reserved  | Reserved  | Reserved
    8      | ARM       | ARM       | ARM       | MLB
    9      | NetCP     | NetCP     | NetCP     | PMMC
    10     | QM_PDSP   | QM_PDSP   | QM_PDSP   | DSS
    11     | PCIe_0    | PCIe_0    | PCIe_0    | MMC
    12     | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
    13     | Reserved  | Reserved  | PCIe_1    | Reserved
    14     | HyperLink | PCIe_1    | HyperLink | Reserved
    15     | Reserved  | Reserved  | TSIP      | Reserved
    -------+-----------+-----------+-----------+---------
    
    NOTE: Few of these might have default configurations, however,
    since most are software configurable, it is better to explicitly
    configure the system to have a known default state.
    
    Without programming these, we end up seeing lack of coherency on certain
    peripherals resulting in inexplicable failures (such as USB peripheral's
    DMA data not appearing on ARM etc and weird workarounds being done by
    drivers including cache flushes which tend to have system wide
    performance impact).
    
    By marking these segments as shared, we also ensure SoC wide coherency
    is enabled.
    Reported-by: default avatarBin Liu <b-liu@ti.com>
    Signed-off-by: default avatarNishanth Menon <nm@ti.com>
    Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
    Reviewed-by: default avatarTom Rini <trini@konsulko.com>
    2283284b
Name
Last commit
Last update
..
include/mach Loading commit data...
Kconfig Loading commit data...
Makefile Loading commit data...
clock.c Loading commit data...
cmd_clock.c Loading commit data...
cmd_ddr3.c Loading commit data...
cmd_mon.c Loading commit data...
cmd_poweroff.c Loading commit data...
config.mk Loading commit data...
ddr3.c Loading commit data...
ddr3_spd.c Loading commit data...
init.c Loading commit data...
keystone.c Loading commit data...
mon.c Loading commit data...
msmc.c Loading commit data...
psc.c Loading commit data...