• Peng Fan's avatar
    imx6: cache: disable L2 before touching Auxiliary Control Register · ad7af5d7
    Peng Fan authored
    According PL310 TRM, Auxiliary Control Register
    "
    The register must be written to using a secure access, and it can be
    read using either a secure or a NS access. If you write to this register
    with a NS access, it results in a write response with a DECERR response,
    and the register is not updated. Writing to this register with the L2
    cache enabled, that is, bit[0] of L2 Control Register set to 1,
    results in a SLVERR.
    "
    
    So If L2 cache is already enabled by ROM, chaning value of ACR
    will cause SLVERR and uboot hang.
    Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
    Cc: Stefano Babic <sbabic@denx.de>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    ad7af5d7
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