• Liu Gang's avatar
    powerpc/corenet_ds: Master module for boot from PCIE · b5f7c873
    Liu Gang authored
    For the powerpc processors with PCIE interface, boot location can be
    configured from one PCIE interface by RCW. The processor booting from PCIE
    can do without flash for u-boot image. The image can be fetched from another
    processor's memory space by PCIE link connected between them.
    
    The processor booting from PCIE is slave, the processor booting from normal
    flash memory space is master, and it can help slave to boot from master's
    memory space.
    
    When boot from PCIE, slave's core should be in holdoff after powered on for
    some specific requirements. Master will release the slave's core at the
    right time by PCIE interface.
    
    Environment and requirement:
    
    master:
        1. NOR flash for its own u-boot image, ucode and ENV space.
        2. Slave's u-boot image is in master NOR flash.
        3. Normally boot from local NOR flash.
        4. Configure PCIE system if needed.
    slave:
        1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
        2. Boot location should be set to one PCIE interface by RCW.
        3. RCW should configure the SerDes, PCIE interfaces correctly.
    	4. Must set all the cores in holdoff by RCW.
    	5. Must be powered on before master's boot.
    
    For the master module, need to finish these processes:
        1. Initialize the PCIE port and address space.
        2. Set inbound PCIE windows covered slave's u-boot image stored in
           master's NOR flash.
    	3. Set outbound windows in order to configure slave's registers
    	   for the core's releasing.
        4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
    	   or "PCIE3" using the following command:
    
    			setenv bootmaster PCIE1
    			saveenv
    Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
    Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
    b5f7c873
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