The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.
This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers will be in separate commits.
Signed-off-by: Chris Zankel <email@example.com>
Signed-off-by: Max Filippov <firstname.lastname@example.org>
Reviewed-by: Simon Glass <email@example.com>
Reviewed-by: Tom Rini <firstname.lastname@example.org>