Commit 28986baf authored by Youness Alaoui's avatar Youness Alaoui
Browse files

Update script and skylake configs for coreboot 4.7

parent 671c69cd
*~
*.bin
*.rom
Librem 15 v3 :
==================================================
4.7-Purism-1
===
- Update to coreboot 4.7
- Update to FSP 2.0
- Add IOMMU support
- Enable TPM support
4.6-a86d1b-Purism-5
====
- Disable running of the GOP driver (Fixes coreinfo not working)
......@@ -27,6 +34,13 @@ Librem 15 v3 :
Librem 13 v2 :
==================================================
4.7-Purism-1
===
- Update to coreboot 4.7
- Update to FSP 2.0
- Add IOMMU support
- Enable TPM support
4.6-a86d1b-Purism-5
====
- Disable running of the GOP driver (Fixes coreinfo not working)
......
#!/bin/bash -e
# depends on : git build-essential bison flex m4 zlib1g-dev gnat libpci-dev libusb-dev libusb-1.0-0-dev dmidecode bsdiff
# depends on : git build-essential bison flex m4 zlib1g-dev gnat libpci-dev libusb-dev libusb-1.0-0-dev dmidecode bsdiff python2.7
# Librem 13 v1 binary blob hashes
BDL_DESCRIPTOR_SHA="be34b19b4de387a07d4fc859d2e4ee44723756f5f54552f236136679b4e52c46"
BDL_DESCRIPTOR_CB_SHA="a6b27231945fd2c1a32e0aeae230da8f4ca8348358d546b1f3dfe9514ae449fc"
BDL_DESCRIPTOR_DISABLED_SHA="976209b5e2d5c19f92de770b1b619ddb38bf587cf01d8c57d70d2abd826d9e11"
BDL_MRC_SHA="dd05ab481e1fe0ce20ade164cf3dbef3c479592801470e6e79faa17624751343"
BDL_REFCODE_SHA="8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4"
BDL_VBIOS_SHA="e1cd1b4f2bd21e036145856e2d092eb47c27cdb4b717c3b182a18d8c0b1d0f01"
# Librem 13 v2 and Librem 15 v3 binary blob hashes
SKL_UCODE_SHA="734b4e20ae3d6d6a610eb75a0ac1682665b3172e2b7725bdf4d3c3f43b24c751"
SKL_OLD_UCODE_SHA="d3625077895f48b96c66aca5b16a3fc260f6db2acc7531bb2dbac53d3886526e"
SKL_DESCRIPTOR_OLD_SHA="754de6400e26583e785d49ba4d78df408b71f57ee5741fb7134dcdfe49636f72"
SKL_UCODE_SHA="9c84936df700d74612a99e6ab581640ecf423d25a0b74a1ea23a6d9872349213"
SKL_DESCRIPTOR_SHA="d5110807c9d67cea6d546ac62125d87042a868177241be4ae17a2dbedef10017"
SKL_DESCRIPTOR_HAP_SHA="642ca36f52aabb5198b82e013bf64a73a5148693a58376fffce322a4d438b524"
SKL_ME_NOCONF_SHA="70f07be7934bdbb215c66455a2b0d32651f3b2ecaf2519d83d8ca9cf475cc366"
SKL_ME_SHA="3042150c7f655293a69bcf886836732fc451439ae551a2babf3173f4f0d9a8d3"
SKL_FSP_SHA="37aa584e8f53dc02e8ed6455f5caf5ae350c560e5bd98b085d99d93c06a3754a"
SKL_VBT_SHA="31654d50e0c783043dbbe62fc1e271b44b6f0379068bf5379deaf2705dae6573"
SKL_FSP_SHA="a7dfec436f5a21a66b5a455775599d73a95170a3446849a34e89a64a2bb69820"
SKL_FSPM_SHA="7a1acc72073969e6753bbfe145f06c3f4d35e2516cb241641eae968705e2cc46"
SKL_FSPS_SHA="0dac94d249473e9d366597fd1f96a0232fb7bf045a3d08f16784961273351822"
SKL_VBT_SHA="51fa214ca44a61b171662d4c2ca6adc1aa3dc6c3d7a24bf9ae5f249f012d61c0"
SKL_VBIOS_SHA="18d861485b86f93dad2b294cebd40b99eb03493d32b514e731ddb8dcf3a1ce83"
# FSP downloadable from Github
SKL_UCODE_URL="https://github.com/platomav/CPUMicrocodes/raw/bfb23e48eb84dff1495d1c8789f133a1b684de27/Intel/cpu406E3_platC0_ver000000C2_2017-11-16_PRD_C6C6F699.bin"
SKL_FSP_URL="https://github.com/IntelFsp/FSP/raw/8267cde09763c0c699704fbae10e6bd121f01b6a/KabylakeFspBinPkg/Fsp.fd"
SKL_VBT_URL="https://github.com/IntelFsp/FSP/raw/8267cde09763c0c699704fbae10e6bd121f01b6a/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
SKL_FSP_SPLIT_URL="https://raw.githubusercontent.com/tianocore/edk2/e8a70885d8f34533b6dd69878fe95a249e9af086/IntelFsp2Pkg/Tools/SplitFspBin.py"
SKL_FSP_SPLIT_SHA="f654f6363de68ad78b1baf8b8e573b53715c3bc76f7f3c23562641e49a7033f3"
# Link found on : http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html
# Update link if it changes and becomes invalid.
SKL_ME_RAR_URL="http://www.mediafire.com/file/1angqt361xdf8k0/"
......@@ -32,10 +36,13 @@ SKL_ME_RAR_SHA="7ce1a75be975cd86c860dde2f114d0a8f7c35802e8bc6623d9ab1dbe285e8954
RAR_NONFREE_SOURCE_URL="https://www.rarlab.com/rar/unrarsrc-5.5.8.tar.gz"
RAR_NONFREE_SOURCE_SHA="9b66e4353a9944bc140eb2a919ff99482dd548f858f5e296d809e8f7cdb2fcf4"
BDL_COREBOOT_BRANCH="librem13v2_sata_fix"
SKL_COREBOOT_BRANCH="librem_4.7"
# Final flashregion_1_bios sha256 hashes
L13V1_COREBOOT_BIOS_SHA="9f75e3b24353cbae88f05ab4900382ed2f928e3c3a661a9250fce7a49874ed11"
L13V2_COREBOOT_BIOS_SHA="cda9d50d6b3967fc6483919b7621256b2200e92ea0af6ee7ed7da0f9e83dec91"
L15V3_COREBOOT_BIOS_SHA="a99b5eb86b655b66fe2be3ddd240e197be1d4a63ef83fe87e6bf6d8784459bd9"
L13V2_COREBOOT_BIOS_SHA="fe12dad83bfa76d56191db5a5091df9e07884aff0dc93e5b3a69ede4f2f4c199"
L15V3_COREBOOT_BIOS_SHA="274d690b67d84e2ddbdf71523661ba4486e35e88250995094cf248b2939a37b6"
die () {
......@@ -81,38 +88,113 @@ check_binary () {
fi
}
check_and_patch_descriptor_bdl () {
if [ ! -f "$BLOB_DIR/descriptor.bin" ]; then
die "Binary blob file 'descriptor.bin' does not exist"
check_and_copy_descriptor_bdl () {
if [ -f "$BLOB_DIR/descriptor.bin" ]; then
sha=$(sha256sum "$BLOB_DIR/descriptor.bin" | awk '{print $1}')
fi
sha=$(sha256sum "$BLOB_DIR/descriptor.bin" | awk '{print $1}')
if [ "$sha" != "$BDL_DESCRIPTOR_SHA" ] && \
[ "$sha" != "$BDL_DESCRIPTOR_CB_SHA" ] && \
[ "$sha" != "$BDL_DESCRIPTOR_DISABLED_SHA" ]; then
die "Extracted binary 'descriptor.bin' has the wrong SHA256 hash"
if [ "$sha" != "$BDL_DESCRIPTOR_SHA" ]; then
cp coreboot-files/descriptor-bdl.bin "$BLOB_DIR/descriptor.bin"
sha=$(sha256sum "$BLOB_DIR/descriptor.bin" | awk '{print $1}')
if [ "$sha" != "$BDL_DESCRIPTOR_SHA" ]; then
die "Binary 'descriptor.bin' has the wrong SHA256 hash"
fi
fi
if [ "$sha" = "$BDL_DESCRIPTOR_DISABLED_SHA" ]; then
dd if=/dev/zero of="$BLOB_DIR/descriptor.bin" count=1 bs=1 seek=296 conv=notrunc
}
check_and_copy_descriptor_skl () {
if [ -f "$BLOB_DIR/descriptor.bin" ]; then
sha=$(sha256sum "$BLOB_DIR/descriptor.bin" | awk '{print $1}')
fi
if [ "$sha" != "$SKL_DESCRIPTOR_SHA" ]; then
cp coreboot-files/descriptor-skl.bin "$BLOB_DIR/descriptor.bin"
sha=$(sha256sum "$BLOB_DIR/descriptor.bin" | awk '{print $1}')
if [ "$sha" != "$SKL_DESCRIPTOR_SHA" ]; then
die "Binary 'descriptor.bin' has the wrong SHA256 hash"
fi
fi
}
check_and_patch_descriptor_skl () {
if [ ! -f "$BLOB_DIR/descriptor.bin" ]; then
die "Binary blob file 'descriptor.bin' does not exist"
check_and_get_vbt () {
if [ -f "$BLOB_DIR/vbt.bin" ]; then
sha=$(sha256sum "$BLOB_DIR/vbt.bin" | awk '{print $1}')
fi
sha=$(sha256sum "$BLOB_DIR/descriptor.bin" | awk '{print $1}')
if [ "$sha" != "$SKL_DESCRIPTOR_SHA" ] && \
[ "$sha" != "$SKL_DESCRIPTOR_HAP_SHA" ] && \
[ "$sha" != "$SKL_DESCRIPTOR_OLD_SHA" ]; then
die "Extracted binary 'descriptor.bin' has the wrong SHA256 hash"
if [ "$sha" != "$SKL_VBT_SHA" ]; then
wget -O "$BLOB_DIR/vbt.bin" "$SKL_VBT_URL"
sha=$(sha256sum "$BLOB_DIR/vbt.bin" | awk '{print $1}')
if [ "$sha" != "$SKL_VBT_SHA" ]; then
die "Downloaded VBT file has the wrong SHA256 hash"
fi
fi
if [ "$sha" = "$SKL_DESCRIPTOR_HAP_SHA" ]; then
dd if=/dev/zero of="$BLOB_DIR/descriptor.bin" count=1 bs=1 seek=258 conv=notrunc
}
check_and_get_skl_microcode () {
if [ -f "$BLOB_DIR/cpu_microcode_blob.bin" ]; then
sha=$(sha256sum "$BLOB_DIR/cpu_microcode_blob.bin" | awk '{print $1}')
fi
if [ "$sha" != "$SKL_UCODE_SHA" ]; then
wget -O "$BLOB_DIR/cpu_microcode_blob.bin" "$SKL_UCODE_URL"
sha=$(sha256sum "$BLOB_DIR/cpu_microcode_blob.bin" | awk '{print $1}')
if [ "$sha" != "$SKL_UCODE_SHA" ]; then
die "Downloaded Intel Microcode Update file has the wrong SHA256 hash"
fi
fi
if [ "$sha" = "$SKL_DESCRIPTOR_OLD_SHA" ]; then
mv "$BLOB_DIR/descriptor.bin" descriptor.old
bspatch descriptor.old "$BLOB_DIR/descriptor.bin" coreboot-files/descriptor-skl.bspatch
rm descriptor.old
}
get_and_split_fsp () {
fsp="fsp.fd"
fsp_M="fsp_M.fd"
fsp_S="fsp_S.fd"
fsp_T="fsp_T.fd"
fspm="fspm.bin"
fsps="fsps.bin"
fsp_split="SplitFspBin.py"
if [ -f "$BLOB_DIR/$fspm" ]; then
fspm_sha=$(sha256sum "$BLOB_DIR/$fspm" | awk '{print $1}')
fi
if [ -f "$BLOB_DIR/$fsps" ]; then
fsps_sha=$(sha256sum "$BLOB_DIR/$fsps" | awk '{print $1}')
fi
# No FSP-M or FSP-S
if [ "$fspm_sha" != "$SKL_FSPM_SHA" ] || [ "$fsps_sha" != "$SKL_FSPS_SHA" ]; then
if [ -f "$BLOB_DIR/$fsp" ]; then
fsp_sha=$(sha256sum "$BLOB_DIR/$fsp" | awk '{print $1}')
fi
# No FSP.fd
if [ "$fsp_sha" != "$SKL_FSP_SHA" ]; then
wget -O "$BLOB_DIR/$fsp" "$SKL_FSP_URL"
fsp_sha=$(sha256sum "$BLOB_DIR/$fsp" | awk '{print $1}')
if [ "$fsp_sha" != "$SKL_FSP_SHA" ]; then
die "Downloaded FSP image has the wrong SHA256 hash"
fi
fi
# No FspSplit
if [ -f "$BLOB_DIR/$fsp_split" ]; then
split_sha=$(sha256sum "$BLOB_DIR/$fsp_split" | awk '{print $1}')
fi
if [ "$split_sha" != "$SKL_FSP_SHA" ]; then
wget -O "$BLOB_DIR/$fsp_split" "$SKL_FSP_SPLIT_URL"
split_sha=$(sha256sum "$BLOB_DIR/$fsp_split" | awk '{print $1}')
if [ "$split_sha" != "$SKL_FSP_SPLIT_SHA" ]; then
die "Downloaded FSP Split Tool has the wrong SHA256 hash"
fi
fi
python2 "$BLOB_DIR/$fsp_split" split -o "$BLOB_DIR" -f "$BLOB_DIR/$fsp"
if [ -f "$BLOB_DIR/$fsp_M" ]; then
mv "$BLOB_DIR/$fsp_M" "$BLOB_DIR/$fspm"
fi
if [ -f "$BLOB_DIR/$fsp_S" ]; then
mv "$BLOB_DIR/$fsp_S" "$BLOB_DIR/$fsps"
fi
fspm_sha=$(sha256sum "$BLOB_DIR/$fspm" | awk '{print $1}')
fsps_sha=$(sha256sum "$BLOB_DIR/$fsps" | awk '{print $1}')
if [ "$fspm_sha" != "$SKL_FSPM_SHA" ] || [ "$fsps_sha" != "$SKL_FSPS_SHA" ]; then
die "Extracted FSP images have the wrong SHA256 hash"
fi
rm -f "$BLOB_DIR/$fsp"
rm -f "$BLOB_DIR/$fsp_split"
rm -f "$BLOB_DIR/$fsp_T"
fi
}
......@@ -226,6 +308,21 @@ flashrom_progress() {
false
fi
}
update_crossgcc_toolchain() {
CURRENT_TOOLCHAIN_VERSION=0
GCC_FILE='util/crossgcc/xgcc/bin/i386-elf-gcc'
TARGET_TOOLCHAIN_VERSION=$(grep -m 1 CROSSGCC_VERSION= util/crossgcc/buildgcc | sed -e 's/^.*="\([0-9]\+\.[0-9]\+\)".*$/\1/')
if [ -f "$GCC_FILE" ]; then
CURRENT_TOOLCHAIN_VERSION=$(${GCC_FILE} --version | grep -m 1 'coreboot toolchain' | sed -e 's/^.*coreboot toolchain v\([0-9]\+\.[0-9]\+\).*$/\1/')
fi
if [ "$CURRENT_TOOLCHAIN_VERSION" != "$TARGET_TOOLCHAIN_VERSION" ]; then
echo "Coreboot toolchain version changed from $CURRENT_TOOLCHAIN_VERSION to $TARGET_TOOLCHAIN_VERSION"
echo "Cleaning crossgcc compiler before rebuilding it"
make crossgcc-clean
fi
make crossgcc-i386
}
DMIDECODE_SERIAL_NUMBER=""
......@@ -237,9 +334,6 @@ if [ ! -d coreboot ]; then
# Apparently if I do the first 'git sup' after I checkout the purism remote, then it looks for the submodules on the purism base URI
git sup
git remote add purism https://code.puri.sm/kakaroto/coreboot.git
git fetch purism
git checkout -b librem purism/librem13v2_sata_fix
git sup
else
cd coreboot
fi
......@@ -285,12 +379,12 @@ elif [ "$machine" = "2" ]; then
echo "The Librem 15 v2 has not yet been ported to Coreboot"
exit 1
elif [ "$machine" = "3" ]; then
BLOB_DIR="3rdparty/blobs/mainboard/purism/librem13v2"
BLOB_DIR="3rdparty/blobs/mainboard/purism/librem_skl"
COREBOOT_FILENAME="coreboot-l13v2.rom"
COREBOOT_BIOS_SHA="$L13V2_COREBOOT_BIOS_SHA"
SKL=1
else
BLOB_DIR="3rdparty/blobs/mainboard/purism/librem15v3"
BLOB_DIR="3rdparty/blobs/mainboard/purism/librem_skl"
COREBOOT_FILENAME="coreboot-l15v3.rom"
COREBOOT_BIOS_SHA="$L15V3_COREBOOT_BIOS_SHA"
SKL=1
......@@ -316,12 +410,13 @@ else
echo "descriptor.bin - The Intel Descriptor - SHA256: $SKL_DESCRIPTOR_SHA"
echo "me.bin - The Intel Management Engine image - SHA256: $SKL_ME_SHA"
echo "vbt.bin - The Video BIOS Table - SHA256: $SKL_VBT_SHA"
echo "fsp.bin - The Intel Firmware Support Package - SHA256: $SKL_FSP_SHA"
echo "fspm.bin - The Intel Firmware Support Package - SHA256: $SKL_FSPM_SHA"
echo "fsps.bin - The Intel Firmware Support Package - SHA256: $SKL_FSPS_SHA"
echo "vgabios.bin - The VGA BIOS - SHA256: $SKL_VBIOS_SHA"
echo "cpu_microcode_blob.bin - The CPU Microcode Update - SHA256: $SKL_UCODE_SHA"
echo ""
echo "If the descriptor.bin file has SHA256 $SKL_DESCRIPTOR_OLD_SHA, it will be automatically patched."
echo "The me.bin can automatically be downloaded, configured and patched so it will match the expected SHA256."
echo "The vbt.bin, fspm.bin and fsps.bin can automatically be downloaded, the me.bin can also be"
echo "downloaded, configured and patched so it will match the expected SHA256."
fi
blobs=0
......@@ -339,10 +434,13 @@ done
if [ ! -d coreboot-files ]; then
git clone https://code.puri.sm/kakaroto/coreboot-files.git
else
(
cd coreboot-files
git pull
)
# For development, just symlink coreboot/coreboot-files to development dir
if [ ! -L coreboot-files ]; then
(
cd coreboot-files
git pull
)
fi
fi
cp coreboot-files/bootsplash.jpg .
......@@ -372,47 +470,39 @@ if [ "$blobs" == "1" ] || [ "$blobs" == "2" ]; then
git checkout skylake
make
)
echo "Using 'sudo flashrom' to grab the local machine's flash content"
sudo ./flashrom/flashrom -p internal:laptop=force_I_want_a_brick,ich_spi_mode=hwseq -r ../coreboot-orig.rom
fi
if [ $SKL -eq 1 ]; then
echo "Using 'sudo dmidecode' to grab the local machine's serial number"
DMIDECODE_SERIAL_NUMBER=$(sudo dmidecode -t 1 | grep "Serial Number" | cut -d' ' -f 3-)
fi
./util/ifdtool/ifdtool -x ../coreboot-orig.rom
rm flashregion_1_bios.bin
mv flashregion_0_flashdescriptor.bin $BLOB_DIR/descriptor.bin
if [ $SKL -eq 0 ]; then
# TODO : Make sure ME image has the right version for Broadwell (10.x)
mv flashregion_2_intel_me.bin $BLOB_DIR/me.bin
check_and_patch_descriptor_bdl
check_and_copy_descriptor_bdl
extract_binary mrc.bin mrc.bin $BDL_MRC_SHA
extract_binary "fallback/refcode" refcode.elf $BDL_REFCODE_SHA
extract_binary pci8086,1616.rom vgabios.bin $BDL_VBIOS_SHA
else
check_and_patch_descriptor_skl
check_and_copy_descriptor_skl
check_binary descriptor.bin $SKL_DESCRIPTOR_SHA
get_and_patch_me_11
check_binary me.bin $SKL_ME_SHA
extract_binary vbt.bin vbt.bin $SKL_VBT_SHA
extract_binary fsp.bin fsp.bin $SKL_FSP_SHA
get_and_split_fsp
check_binary fspm.bin $SKL_FSPM_SHA
check_binary fsps.bin $SKL_FSPS_SHA
check_and_get_vbt
check_binary vbt.bin $SKL_VBT_SHA
check_and_get_skl_microcode
check_binary cpu_microcode_blob.bin $SKL_UCODE_SHA
extract_binary pci8086,1916.rom vgabios.bin $SKL_VBIOS_SHA
if [ -f $BLOB_DIR/cpu_microcode_blob.bin ]; then
sha=$(sha256sum $BLOB_DIR/cpu_microcode_blob.bin | awk '{print $1}')
fi
if [ "$sha" != "$SKL_UCODE_SHA" ]; then
./util/cbfstool/cbfstool ../coreboot-orig.rom extract -n cpu_microcode_blob.bin -f $BLOB_DIR/cpu_microcode_blob.bin
sha=$(sha256sum $BLOB_DIR/cpu_microcode_blob.bin | awk '{print $1}')
if [ "$sha" != "$SKL_UCODE_SHA" ]; then
if [ "$sha" == "$SKL_OLD_UCODE_SHA" ]; then
echo "The CPU microcode update on your machine is an outdated version"
echo "Please download the latest microcode update from : https://downloadcenter.intel.com/download/26925/Linux-Processor-Microcode-Data-File?product=122139"
echo "Then place the intel-ucode/06-4e-03 file from the archive into coreboot/$BLOB_DIR/cpu_microcode_blob.bin"
die ""
else
die "Extracted binary has the wrong SHA256 hash"
fi
fi
fi
./util/cbfstool/cbfstool ../coreboot-orig.rom extract -n serial_number -f serial_number.txt &> /dev/null && HAVE_SERIAL="yes"
fi
else
......@@ -420,17 +510,18 @@ else
if [ ! -f "$BLOB_DIR/me.bin" ]; then
die "Binary blob file 'me.bin' does not exist"
fi
check_and_patch_descriptor_bdl
check_and_copy_descriptor_bdl
check_binary mrc.bin $BDL_MRC_SHA
check_binary refcode.elf $BDL_REFCODE_SHA
check_binary vgabios.bin $BDL_VBIOS_SHA
else
check_and_patch_descriptor_skl
check_and_copy_descriptor_skl
check_binary descriptor.bin $SKL_DESCRIPTOR_SHA
get_and_patch_me_11
check_binary me.bin $SKL_ME_SHA
check_binary vbt.bin $SKL_VBT_SHA
check_binary fsp.bin $SKL_FSP_SHA
check_binary fspm.bin $SKL_FSPM_SHA
check_binary fsps.bin $SKL_FSPS_SHA
check_binary vgabios.bin $SKL_VBIOS_SHA
check_binary cpu_microcode_blob.bin $SKL_UCODE_SHA
fi
......@@ -487,7 +578,29 @@ else
rm -f serial_number.txt
fi
make crossgcc-i386
if [ $SKL -eq 1 ]; then
# Need to fetch origin in order to get all upstream tags
# which are used when doing 'git describe' (it affects final hash)
git fetch origin
git fetch purism
# checkout master so we can delete the librem branch
git checkout master
# delete it, in case it's our first run, do || true
git branch -D librem || true
git checkout -b librem purism/$SKL_COREBOOT_BRANCH
# need to update submodules after the checkout
git sup
else
git fetch origin
git fetch purism
git checkout master
git branch -D librem || true
git checkout -b librem purism/$BDL_COREBOOT_BRANCH
git sup
fi
update_crossgcc_toolchain
make clean
make
./util/ifdtool/ifdtool -x build/coreboot.rom
......
......@@ -7,7 +7,7 @@
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION="4.6-a86d1b-Purism-5"
CONFIG_LOCALVERSION="4.7-Purism-1"
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
......@@ -51,10 +51,10 @@ CONFIG_BOOTSPLASH_FILE="bootsplash.jpg"
# CONFIG_VENDOR_BACHMANN is not set
# CONFIG_VENDOR_BAP is not set
# CONFIG_VENDOR_BCOM is not set
# CONFIG_VENDOR_BIFFEROS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BROADCOM is not set
# CONFIG_VENDOR_COMPAQ is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CUBIETECH is not set
# CONFIG_VENDOR_DIGITALLOGIC is not set
# CONFIG_VENDOR_DMP is not set
......@@ -103,16 +103,16 @@ CONFIG_VENDOR_PURISM=y
# CONFIG_VENDOR_TYAN is not set
# CONFIG_VENDOR_VIA is not set
# CONFIG_VENDOR_WINENT is not set
# CONFIG_VENDOR_WINNET is not set
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="purism/librem13v2"
CONFIG_MAINBOARD_DIR="purism/librem_skl"
CONFIG_MAINBOARD_PART_NUMBER="Librem 13 v2"
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_MAINBOARD_VENDOR="Purism"
CONFIG_MAX_CPUS=8
CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0
CONFIG_FSP_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp.bin"
CONFIG_CBFS_SIZE=0x5c0000
CONFIG_CBFS_SIZE=0xe00000
CONFIG_UART_FOR_CONSOLE=0
CONFIG_PAYLOAD_CONFIGFILE=""
CONFIG_VGA_BIOS_ID="8086,1916"
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
......@@ -127,20 +127,28 @@ CONFIG_HAVE_IFD_BIN=y
CONFIG_HAVE_ME_BIN=y
CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
# CONFIG_POST_IO is not set
CONFIG_DEVICETREE="devicetree.cb"
CONFIG_DEVICETREE="variants/librem13v2/devicetree.cb"
CONFIG_MAX_REBOOT_CNT=3
# CONFIG_HAVE_GBE_BIN is not set
CONFIG_ID_SECTION_OFFSET=0x80
# CONFIG_POST_DEVICE is not set
CONFIG_VARIANT_DIR="librem13v2"
# CONFIG_VBOOT is not set
CONFIG_MAINBOARD_FAMILY="Librem 13"
CONFIG_TPM_PIRQ=0x0
CONFIG_DIMM_MAX=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_FMDFILE=""
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_FMDFILE=""
CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
# CONFIG_HAVE_GBE_BIN is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Librem 13 v2"
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fspm.bin"
CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsps.bin"
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
CONFIG_CPU_ADDR_BITS=36
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAINBOARD_VERSION="2.0"
......@@ -150,9 +158,9 @@ CONFIG_BOARD_PURISM_LIBREM13_V2=y
# CONFIG_BOARD_PURISM_LIBREM15_V3 is not set
CONFIG_PCIEXP_L1_SUB_STATE=y
# CONFIG_NO_POST is not set
CONFIG_PRE_GRAPHICS_DELAY=0
CONFIG_CPU_MICROCODE_CBFS_LEN=0x18000
CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFE115A0
CONFIG_BOARD_PURISM_BASEBOARD_LIBREM_SKL=y
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
......@@ -162,6 +170,7 @@ CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
......@@ -179,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# SoC
#
# CONFIG_SOC_BROADCOM_CYGNUS is not set
CONFIG_CPU_SPECIFIC_OPTIONS=y
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_RAMTOP=0x200000
CONFIG_HEAP_SIZE=0x80000
CONFIG_RAMBASE=0x100000
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x200000
CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
# CONFIG_SOC_BROADCOM_CYGNUS is not set
# CONFIG_SOC_INTEL_GLK is not set
CONFIG_SOC_INTEL_COMMON_RESET=y
CONFIG_PCR_BASE_ADDRESS=0xfd000000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_SOC_INTEL_COMMON_LPSS_CLOCK_MHZ=120
CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set
CONFIG_HEAP_SIZE=0x80000
# CONFIG_NHLT_MAX98357 is not set
# CONFIG_NHLT_DA7219 is not set
# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set
CONFIG_SMM_RESERVED_SIZE=0x200000
CONFIG_CPU_BCLK_MHZ=100
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set
CONFIG_CHIPSET_BOOTBLOCK_INCLUDE="soc/intel/skylake/bootblock/timestamp.inc"
CONFIG_IED_REGION_SIZE=0x400000
......@@ -204,7 +220,30 @@ CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_PCIEXP_CLK_PM=y
# CONFIG_SERIAL_CPU_INIT is not set
CONFIG_SERIRQ_CONTINUOUS_MODE=y
# CONFIG_UART_DEBUG is not set
CONFIG_MAX_ROOT_PORTS=24
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
CONFIG_STACK_SIZE=0x1000
CONFIG_CONSOLE_CBMEM=y
CONFIG_UART_PCI_ADDR=0x0
CONFIG_SOC_INTEL_SKYLAKE=y
# CONFIG_SOC_INTEL_KABYLAKE is not set
CONFIG_MAINBOARD_USES_FSP2_0=y
CONFIG_USE_FSP2_0_DRIVER=y
CONFIG_BOOTBLOCK_RESETS="soc/intel/common/reset.c"
# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set
# CONFIG_SKYLAKE_SOC_PCH_H is not set
# CONFIG_NHLT_DMIC_2CH is not set
# CONFIG_NHLT_DMIC_4CH is not set
# CONFIG_NHLT_NAU88L25 is not set
# CONFIG_NHLT_SSM4567 is not set
# CONFIG_NHLT_RT5514 is not set
# CONFIG_NHLT_RT5663 is not set
# CONFIG_NHLT_MAX98927 is not set
CONFIG_CAR_NEM_ENHANCED=y
# CONFIG_USE_SKYLAKE_FSP_CAR is not set
CONFIG_SKIP_FSP_CAR=y
# CONFIG_NO_FADT_8042 is not set
CONFIG_SOC_INTEL_COMMON=y
#
......@@ -216,23 +255,45 @@ CONFIG_SOC_INTEL_COMMON_BLOCK=y
# Intel SoC Common IP Code
#
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
# CONFIG_INTEL_CAR_NEM is not set
# CONFIG_INTEL_CAR_CQOS is not set
CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_CSE is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
# CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_I2C_DEBUG is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
CONFIG_SA_PCIEX_LENGTH=0x4000000
CONFIG_PCIEX_LENGTH_64MB=y
......@@ -241,48 +302,15 @@ CONFIG_SA_ENABLE_DPR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
CONFIG_SOC_INTEL_COMMON_SPI_FLASH_PROTECT=y
CONFIG_MRC_SETTINGS_CACHE_BASE=0xfffe0000
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_HAS_RECOVERY_MRC_CACHE is not set
# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set
# CONFIG_DISPLAY_MTRRS is not set
# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
# CONFIG_ACPI_CONSOLE is not set
# CONFIG_SOC_INTEL_COMMON_LPSS_I2C is not set
# CONFIG_MMA is not set
CONFIG_ADD_VBT_DATA_FILE=y