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Haibo Chen authored
Description: uSDHC AHB_BUS and IPG_CLK clocks must be synchronized. Due to current physical design implementation, AHB_BUS and IPG_CLK must come from same clock source to maintain clock sync. Workaround: Set AHB_BUS and IPG_CLK to clock source from PLL1. After sys1_pll_266m gate off/on, seems need to sync the USDHC AHB bus and USDHC IPG_clk again. (Here usdhc AHB BUS source from nand_usdhc_bus.) This sync is handle by hardware, and maybe need some time, during this sync period, usdhc operation may has issue. I just double check our local v5.10 branch, already revert the commit b04383b6 (clk: imx8mq: Define gates for pll1/2 fixed dividers). So to fix this issue, one method is revert this patch, another method is keep the 'nand_usdhc_bus' always on. Add change like this: Signed-off-by: Angus Ainslie <angus@akkea.ca>
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