1. 30 Jun, 2020 12 commits
  2. 24 Jun, 2020 9 commits
  3. 22 Jun, 2020 6 commits
  4. 17 Jun, 2020 1 commit
  5. 02 Jun, 2020 3 commits
  6. 21 May, 2020 5 commits
  7. 20 May, 2020 1 commit
    • Robert Beckett's avatar
      ARM: dts/imx6q-bx50v3: Set display interface clock parents · 665e7c73
      Robert Beckett authored
      
      
      Avoid LDB and IPU DI clocks both using the same parent. LDB requires
      pasthrough clock to avoid breaking timing while IPU DI does not.
      
      Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
      and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.
      
      This fixes an issue where attempting atomic modeset while using
      HDMI and display port at the same time causes LDB clock programming
      to destroy the programming of HDMI that was done during the same
      modeset.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarRobert Beckett <bob.beckett@collabora.com>
      [Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
       originally chosen by Robert Beckett to avoid affecting eMMC clock
       by DRM atomic updates]
      Signed-off-by: default avatarIan Ray <ian.ray@ge.com>
      [Squash Robert's and Ian's commits for bisectability, update patch
       description and add stable tag]
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      665e7c73
  8. 19 May, 2020 1 commit
    • Fredrik Strupe's avatar
      ARM: 8977/1: ptrace: Fix mask for thumb breakpoint hook · 3866f217
      Fredrik Strupe authored
      call_undef_hook() in traps.c applies the same instr_mask for both 16-bit
      and 32-bit thumb instructions. If instr_mask then is only 16 bits wide
      (0xffff as opposed to 0xffffffff), the first half-word of 32-bit thumb
      instructions will be masked out. This makes the function match 32-bit
      thumb instructions where the second half-word is equal to instr_val,
      regardless of the first half-word.
      
      The result in this case is that all undefined 32-bit thumb instructions
      with the second half-word equal to 0xde01 (udf #1
      
      ) work as breakpoints
      and will raise a SIGTRAP instead of a SIGILL, instead of just the one
      intended 16-bit instruction. An example of such an instruction is
      0xeaa0de01, which is unallocated according to Arm ARM and should raise a
      SIGILL, but instead raises a SIGTRAP.
      
      This patch fixes the issue by setting all the bits in instr_mask, which
      will still match the intended 16-bit thumb instruction (where the
      upper half is always 0), but not any 32-bit thumb instructions.
      
      Cc: Oleg Nesterov <oleg@redhat.com>
      Signed-off-by: default avatarFredrik Strupe <fredrik@strupe.net>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      3866f217
  9. 15 May, 2020 2 commits