1. 30 Jun, 2020 9 commits
  2. 24 Jun, 2020 7 commits
  3. 22 Jun, 2020 4 commits
  4. 17 Jun, 2020 1 commit
  5. 02 Jun, 2020 2 commits
  6. 21 May, 2020 5 commits
  7. 20 May, 2020 1 commit
    • Robert Beckett's avatar
      ARM: dts/imx6q-bx50v3: Set display interface clock parents · 665e7c73
      Robert Beckett authored
      
      
      Avoid LDB and IPU DI clocks both using the same parent. LDB requires
      pasthrough clock to avoid breaking timing while IPU DI does not.
      
      Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
      and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.
      
      This fixes an issue where attempting atomic modeset while using
      HDMI and display port at the same time causes LDB clock programming
      to destroy the programming of HDMI that was done during the same
      modeset.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarRobert Beckett <bob.beckett@collabora.com>
      [Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
       originally chosen by Robert Beckett to avoid affecting eMMC clock
       by DRM atomic updates]
      Signed-off-by: default avatarIan Ray <ian.ray@ge.com>
      [Squash Robert's and Ian's commits for bisectability, update patch
       description and add stable tag]
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      665e7c73
  8. 15 May, 2020 2 commits
  9. 12 May, 2020 1 commit
    • Tony Lindgren's avatar
      ARM: dts: Fix wrong mdio clock for dm814x · fb6823a6
      Tony Lindgren authored
      Recent PTP-specific cpsw driver changes started exposing an issue on at
      at least j5eco-evm:
      
      Unhandled fault: external abort on non-linefetch (0x1008) at 0xf0169004
      ...
      (davinci_mdio_runtime_suspend) from [<c063f2a4>] (__rpm_callback+0x84/0x154)
      (__rpm_callback) from [<c063f394>] (rpm_callback+0x20/0x80)
      (rpm_callback) from [<c063f4f0>] (rpm_suspend+0xfc/0x6ac)
      (rpm_suspend) from [<c0640af0>] (pm_runtime_work+0x88/0xa4)
      (pm_runtime_work) from [<c0155338>] (process_one_work+0x228/0x568)
      ...
      
      Let's fix the issue by using the correct mdio clock as suggested by
      Grygorii Strashko <grygorii.strashko@ti.com>.
      
      The DM814_ETHERNET_CPGMAC0_CLKCTRL clock is the interconnect target module
      clock and managed by ti-sysc.
      
      Fixes: 6398f347
      
       ("ARM: dts: Configure interconnect target module for dm814x cpsw")
      Cc: Grygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      fb6823a6
  10. 11 May, 2020 1 commit
  11. 08 May, 2020 1 commit
    • Grygorii Strashko's avatar
      ARM: dts: am437x: fix networking on boards with ksz9031 phy · 2de00450
      Grygorii Strashko authored
      Since commit bcf3440c ("net: phy: micrel: add phy-mode support for the
      KSZ9031 PHY") the networking is broken on boards:
       am437x-gp-evm
       am437x-sk-evm
       am437x-idk-evm
      
      All above boards have phy-mode = "rgmii" and this is worked before, because
      KSZ9031 PHY started with default RGMII internal delays configuration (TX
      off, RX on 1.2 ns) and MAC provided TX delay. After above commit, the
      KSZ9031 PHY starts handling phy mode properly and disables RX delay, as
      result networking is become broken.
      
      Fix it by switching to phy-mode = "rgmii-rxid" to reflect previous
      behavior.
      
      Cc: Oleksij Rempel <o.rempel@pengutronix.de>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Philippe Schenker <philippe.schenker@toradex.com>
      Fixes: bcf3440c
      
       ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY")
      Reviewed-by: default avatarPhilippe Schenker <philippe.schenker@toradex.com>
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      2de00450
  12. 07 May, 2020 1 commit
    • Grygorii Strashko's avatar
      ARM: dts: am57xx: fix networking on boards with ksz9031 phy · 820f8a87
      Grygorii Strashko authored
      Since commit bcf3440c ("net: phy: micrel: add phy-mode support for the
      KSZ9031 PHY") the networking is broken on boards:
       am571x-idk
       am572x-idk
       am574x-idk
       am57xx-beagle-x15
      
      All above boards have phy-mode = "rgmii" and this is worked before because
      KSZ9031 PHY started with default RGMII internal delays configuration (TX
      off, RX on 1.2 ns) and MAC provided TX delay. After above commit, the
      KSZ9031 PHY starts handling phy mode properly and disables RX delay, as
      result networking is become broken.
      
      Fix it by switching to phy-mode = "rgmii-rxid" to reflect previous
      behavior.
      
      Cc: Oleksij Rempel <o.rempel@pengutronix.de>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Philippe Schenker <philippe.schenker@toradex.com>
      Fixes: bcf3440c
      
       ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY")
      Reviewed-by: default avatarPhilippe Schenker <philippe.schenker@toradex.com>
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      820f8a87
  13. 05 May, 2020 2 commits
    • Tony Lindgren's avatar
      ARM: dts: omap4-droid4: Fix occasional lost wakeirq for uart1 · 738b150e
      Tony Lindgren authored
      
      
      Looks like using the UART CTS pin does not always trigger for a wake-up
      when the SoC is idle.
      
      This is probably because the modem first uses gpio_149 to signal the SoC
      that data will be sent, and the CTS will only get used later when the
      data transfer is starting.
      
      Let's fix the issue by configuring the gpio_149 pad as the wakeirq for
      UART. We have gpio_149 managed by the USB PHY for powering up the right
      USB mode, and after that, the gpio gets recycled as the modem wake-up
      pin. If needeed, the USB PHY can also later on be configured to use
      gpio_149 pad as the wakeirq as a shared irq.
      
      Let's also configure the missing properties for uart-has-rtscts and
      current-speed for the modem port while at it. We already configure the
      hardware flow control pins with uart1_pins pinctrl setting.
      
      Cc: maemo-leste@lists.dyne.org
      Cc: Merlijn Wajer <merlijn@wizzup.org>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Sebastian Reichel <sre@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      738b150e
    • Tony Lindgren's avatar
      ARM: dts: omap4-droid4: Fix flakey wlan by disabling internal pull for gpio · 30fa60c6
      Tony Lindgren authored
      
      
      The wlan on droid4 is flakey on some devices, and experiments have shown this
      gets fixed if we disable the internal pull for wlan gpio interrupt line.
      
      The symptoms are that the wlan connection is very slow and almost useless
      with lots of wlcore firmware reboot warnings in the dmesg.
      
      In addition to configuring the wlan gpio pulls, let's also configure the rest
      of the wlan sd pins. We have not configured those eariler as we're booting
      using kexec.
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      30fa60c6
  14. 29 Apr, 2020 1 commit
  15. 28 Apr, 2020 1 commit
  16. 27 Apr, 2020 1 commit