- 24 Jun, 2020 2 commits
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Andrew Jeffery authored
[ Upstream commit fa4c8ec6 ] Fixes the following warnings for both g5 and g6 SoCs: arch/arm/boot/dts/aspeed-g5.dtsi:376.19-381.8: Warning (unit_address_vs_reg): /ahb/apb/lpc@1e789000/lpc-bmc@0/kcs1@0: node has a unit name, but no reg property Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Sasha Levin <sashal@kernel.org>
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Eddie James authored
[ Upstream commit c998f40f ] According to ASPEED, FTTMR010 is not intended to be used in the AST2600. The arch timer should be used, but Linux doesn't enable high-res timers without being assured that the arch timer is always on, so set that property in the devicetree. The FTTMR010 device is described by set to disabled. This fixes highres timer support for AST2600. Fixes: 2ca5646b ("ARM: dts: aspeed: Add AST2600 and EVB") Signed-off-by:
Eddie James <eajames@linux.ibm.com> Reviewed-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Sasha Levin <sashal@kernel.org>
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- 15 Mar, 2020 1 commit
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Tao Ren authored
Add USB components and according pin groups in aspeed-g6 dtsi. Signed-off-by:
Tao Ren <rentao.bupt@gmail.com> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Felipe Balbi <balbi@kernel.org>
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- 08 Jan, 2020 1 commit
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Joel Stanley authored
The FIS nodes were placed incorrectly in the device tree. Fixes: 0fe4e304 ("ARM: dts: aspeed-g6: Describe FSI masters") Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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- 17 Dec, 2019 1 commit
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Andrew Jeffery authored
arch/arm/boot/dts/aspeed-g6.dtsi:204.28-208.6: Warning (simple_bus_reg): /ahb/apb/watchdog@1e7850C0: simple-bus unit address format error, expected "1e7850c0" Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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- 07 Nov, 2019 1 commit
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Joel Stanley authored
The AST2600 has 8 32-bit timers on the APB bus. Reviewed-by:
Cédric Le Goater <clg@kaod.org> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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- 01 Nov, 2019 10 commits
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Joel Stanley authored
The AST2600 has five UARTs. Add UART 1 to 4. Tested-by:
Eddie James <eajames@linux.ibm.com> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Joel Stanley authored
The upstream clock for the I2C buses is APB2. Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Joel Stanley authored
The ast2600 has two FSI masters on the APB. Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Andrew Jeffery authored
This way enabling the MDIO controllers automatically requests the right pinmux configuration. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Cédric Le Goater authored
Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Brad Bishop authored
Everything is the same as G5, except the devices have their own interrupt now. Acked-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Joel Stanley authored
The AST2600 has two VUART devices. Reviewed-by:
Eddie James <eajames@linux.ibm.com> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Joel Stanley authored
The AST2600 has 16 I2C buses each with their own global IRQ line. Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Rashmica Gupta authored
The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs. Signed-off-by:
Rashmica Gupta <rashmica.g@gmail.com> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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Andrew Jeffery authored
Enable the eMMC controller and limit it to 52MHz to avoid the host controller reporting bus error conditions. Reviewed-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au>
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- 12 Sep, 2019 2 commits
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Andrew Jeffery authored
Add them in their own dtsi and include it in aspeed-g6.dtsi to isolate the cruft. Link: https://lore.kernel.org/r/20190911165614.31641-2-joel@jms.id.auSigned-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Joel Stanley authored
The AST2600 is a new SoC by ASPEED. It contains a dual core Cortex A7 CPU and shares many periperhals with the existing AST2400 and AST2500. Link: https://lore.kernel.org/r/20190911165614.31641-1-joel@jms.id.auReviewed-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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