1. 30 Jun, 2020 2 commits
  2. 23 Jun, 2019 1 commit
  3. 30 Jan, 2019 1 commit
  4. 05 Nov, 2018 1 commit
  5. 13 Sep, 2018 2 commits
    • Rob Herring's avatar
      ARM: dts: bcm: Fix SPI bus warnings · ab0b47d2
      Rob Herring authored
      dtc has new checks for SPI buses. Fix the warnings in node names.
      
      arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dtb: Warning (spi_bus_bridge): /axi@18000000/qspi@27200: node name for SPI buses should be 'spi'
      arch/arm/boot/dts/bcm958525er.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
      arch/arm/boot/dts/bcm958525xmc.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
      arch/arm/boot/dts/bcm958622hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
      arch/arm/boot/dts/bcm958625hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
      arch/arm/boot/dts/bcm988312hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
      
      Cc: Ray Jui <rjui@broadcom.com>
      Cc: Scott Branden <sbranden@broadcom.com>
      Cc: Jon Mason <jonmason@broadcom.com>
      Cc: bcm-kernel-feedback-list@broadcom.com
      Signed-off-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      ab0b47d2
    • Florian Fainelli's avatar
      ARM: dts: NSP: Wire up switch interrupts · ccf8b4e4
      Florian Fainelli authored
      The Switch Register Access Block (SRAB) has one interrupt for link state
      change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
      and sleep timer interrupts for each management ports (5,7,8). Wire those
      up so we can utilize them to speed up link resolution.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      ccf8b4e4
  6. 18 Jun, 2018 2 commits
  7. 27 Nov, 2017 1 commit
    • Florian Fainelli's avatar
      ARM: dts: NSP: Fix PPI interrupt types · 5f1aa51c
      Florian Fainelli authored
      Booting a kernel results in the kernel warning us about the following
      PPI interrupts configuration:
      [    0.105127] smp: Bringing up secondary CPUs ...
      [    0.110545] GIC: PPI11 is secure or misconfigured
      [    0.110551] GIC: PPI13 is secure or misconfigured
      
      Fix this by using the appropriate edge configuration for PPI11 and
      PPI13, this is similar to what was fixed for Northstar (BCM5301X) in
      commit 0e34079c ("ARM: dts: BCM5301X: Correct GIC_PPI interrupt
      flags").
      
      Fixes: 7b2e987d ("ARM: NSP: add minimal Northstar Plus device tree")
      Fixes: 1a9d53ca ("ARM: dts: NSP: Add TWD Support to DT")
      Acked-by: default avatarJon Mason <jon.mason@broadcom.com>
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      5f1aa51c
  8. 19 Oct, 2017 1 commit
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  21. 12 Feb, 2016 5 commits
  22. 11 Feb, 2016 1 commit