Register the ARM generic cpuidle driver as a cooling device.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

For cpuidle_cooling_runtime() returning 0, no idle-injection is
applied. For an idle injection percentage of 0, this makes sense. But
this happends for the idle injection percentage of 100 too, which is
wrong.

The documented calculation: ((idle_cycle * 100) / state) - idle_cycle
results 0 for state being 100. For "state" from 0 to 99, the thermal
driver throttles accordingly and keeps the CPUs cool. When switching
to 100, it stops cooling, we see a jump up in temperature and the CPU
heats up until it shuts down.

Work around this problem by keeping the "state" at 99 for calculations,
never reaching 100. The user interface still reaches 100, but there
is no formal connection to actual data and the UI. It's just a unified
range that can be implemented in various ways.

Only when the cpufreq strategy is used, it gets defined in cpu_cooling.c

This has to be considered a workaround, fixing the build for the cpuidle
thermal driver.

The cpu idle cooling driver performs synchronized idle injection across all
cpus belonging to the same cluster and offers a new method to cool down a SoC.

Each cluster has its own idle cooling device, each core has its own idle
injection thread, each idle injection thread uses play_idle to enter idle.  In
order to reach the deepest idle state, each cooling device has the idle
injection threads synchronized together.

It has some similarity with the intel power clamp driver but it is actually
designed to work on the ARM architecture via the DT with a mathematical proof
with the power model which comes with the Documentation.

The idle injection cycle is fixed while the running cycle is variable. That
allows to have control on the device reactivity for the user experience. At
the mitigation point the idle threads are unparked, they play idle the
specified amount of time and they schedule themselves. The last thread sets
the next idle inject...

The next changes will add new way to cool down a CPU. In order to
sanitize and make the overall cpu cooling code consistent and robust
we must prevent the cpu cooling devices to co-exists with the same
purpose at the same time in the kernel.

Make the CPU cooling device a choice in the Kconfig, so only one CPU
cooling strategy can be chosen.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Provide some documentation for the idle injection cooling effect in
order to let people to understand the rational of the approach for the
idle injection CPU cooling device.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Right now in upstream imx8m cpufreq support just lists a common subset
of OPPs because the higher ones should only be attempted after checking
speed grading in fuses.

Add a small driver which checks speed grading from nvmem cells before
registering cpufreq-dt.

This driver allows unlocking all frequencies for imx8mm and imx8mq and
could be applied to other chips like imx7d

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

Add the cpu-sleep idle state with all the necessary parameters and also add
the cpu-idle-states to the cpu nodes.

The 'broken-wake-request-signals' property is used to let the irq-imx-gpcv2
driver know that the wake request signals from GIC are not linked to the
GPC at all and, therefore, the driver should  make use of the dedicated
workaround to explicitly wake up the target core on every IPI.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
breaks cpuidle support due to inability to wake target cores on IPIs.

Here is the link to the errata (see e11171):

https://www.nxp.com/docs/en/errata/IMX8MDQLQ_0N14W.pdf



Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by
setting 12th bit in IOMUX_GPR1 register. In order to control the target cores
only, that is, not waking up all the cores every time, we can unmask/mask the
IRQ 32 in the first GPC IMR register. So basically we can leave the IOMUX_GPR1
12th bit always set and just play with the masking and unmasking the IRO 32 for
each independent core.

Since EL3 is the one that deals with powering down/up the cores, and since the
cores wake up in EL3, EL3 should be the one to control the IMRs in this case.
This implies we need to get into EL3 on every IPI to do the unmasking, leaving
the masking to be done on the power-up sequence by the core itself.

In order to be able to get into EL3 on each IPI, we 'hijack' the registered smp
cross call handler, in this case the gic_raise_softirq which is registered by
the irq-gic-v3 driver and register our own handler instead. This new handler is
basically a wrapper over the hijacked handler plus the call into EL3.

To get into EL3, we use a custom vendor SIP id added just for this purpose.

All of this is conditional for i.MX8MQ only.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

enable cpuidle

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

We need to rename the exported rsi_ functions so they don't conflict
with the mainline driver.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Spoof low power mode as it interferes with thoughput

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

To enable the diversity set the module parameter antenna_diversity=1

insmod rsi_91x.ko rsi_zone_enabled=1 dev_oper_mode=13 antenna_diversity=1

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

add the redpine module driver to the build

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Add the Redpine driver for RS9116 module

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Specify which regulator is used for cpufreq DVFS.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Add a VID:PID for the BroadModi BM818 M.2 card

Co-developed-by:  <bob.ham@puri.sm>
Signed-off-by:  <bob.ham@puri.sm>
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Without a VBUS supply the dwc3 driver won't go into otg mode.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Due to current spikes during boot the USB-C VBUS can get drawn down too
low causing the bq25890 to reset the board. Allow VBUS to drop a bit
further to make allowance for thses spikes.

Signed-off-by: Eric Kuzmenko <eric.kuzmenko@puri.sm>
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

The bq25890 has low voltage protection on VIN. Allow the register
to be set from the device tree.

Signed-off-by: Eric Kuzmenko <eric.kuzmenko@puri.sm>
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

This uses

 - our nwl mipi dsi controller driver
 - our mixel dphy driver
 - a forward port from NXPs dcss driver from our 4.18 tree
   (which we got from their 4.9/4.14 trees)
 - a forward port NXPs patches to the imx-display-subsystem driver
   from our 4.18 tree (which we got from their 4.9/4.14 trees)

ctxld fails during boot due to its irqsteer dependency. Make us undo
less stuff so that probing again works later on (instead of hanging the
boot).

TODO: check if this works on 4.18 too

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

We're returning != 0 on error

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

See 463659a0



Signed-off-by: Guido Günther <guido.gunther@puri.sm>

According to 4.18 we have B0. Need to check what to do about busfreq

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Like in 1ef2917d



Signed-off-by: Guido Günther <guido.gunther@puri.sm>

like in f53705fd



Signed-off-by: Guido Günther <guido.gunther@puri.sm>

We don't have anything feeding these and they cause trouble when
rebasing on linux-next so drop them.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

from NXPs kernel

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

We don't need it atm.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>