init.c 48.9 KB
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/*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
 *  arch/sparc64/mm/init.c
 *
 *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */
 
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#include <linux/module.h>
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#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/slab.h>
#include <linux/initrd.h>
#include <linux/swap.h>
#include <linux/pagemap.h>
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#include <linux/poison.h>
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#include <linux/fs.h>
#include <linux/seq_file.h>
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#include <linux/kprobes.h>
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#include <linux/cache.h>
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#include <linux/sort.h>
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#include <asm/head.h>
#include <asm/system.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/iommu.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
#include <asm/starfire.h>
#include <asm/tlb.h>
#include <asm/spitfire.h>
#include <asm/sections.h>
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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extern void device_scan(void);

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#define MAX_PHYS_ADDRESS	(1UL << 42UL)
#define KPTE_BITMAP_CHUNK_SZ	(256UL * 1024UL * 1024UL)
#define KPTE_BITMAP_BYTES	\
	((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)

unsigned long kern_linear_pte_xor[2] __read_mostly;

/* A bitmap, one bit for every 256MB of physical memory.  If the bit
 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
 */
unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];

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/* A special kernel TSB for 4MB and 256MB linear mappings.  */
struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];

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#define MAX_BANKS	32

static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
static int pavail_ents __initdata;
static int pavail_rescan_ents __initdata;

static int cmp_p64(const void *a, const void *b)
{
	const struct linux_prom64_registers *x = a, *y = b;

	if (x->phys_addr > y->phys_addr)
		return 1;
	if (x->phys_addr < y->phys_addr)
		return -1;
	return 0;
}

static void __init read_obp_memory(const char *property,
				   struct linux_prom64_registers *regs,
				   int *num_ents)
{
	int node = prom_finddevice("/memory");
	int prop_size = prom_getproplen(node, property);
	int ents, ret, i;

	ents = prop_size / sizeof(struct linux_prom64_registers);
	if (ents > MAX_BANKS) {
		prom_printf("The machine has more %s property entries than "
			    "this kernel can support (%d).\n",
			    property, MAX_BANKS);
		prom_halt();
	}

	ret = prom_getproperty(node, property, (char *) regs, prop_size);
	if (ret == -1) {
		prom_printf("Couldn't get %s property from /memory.\n");
		prom_halt();
	}

	/* Sanitize what we got from the firmware, by page aligning
	 * everything.
	 */
	for (i = 0; i < ents; i++) {
		unsigned long base, size;

		base = regs[i].phys_addr;
		size = regs[i].reg_size;
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		size &= PAGE_MASK;
		if (base & ~PAGE_MASK) {
			unsigned long new_base = PAGE_ALIGN(base);

			size -= new_base - base;
			if ((long) size < 0L)
				size = 0UL;
			base = new_base;
		}
		regs[i].phys_addr = base;
		regs[i].reg_size = size;
	}
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	for (i = 0; i < ents; i++) {
		if (regs[i].reg_size == 0UL) {
			int j;

			for (j = i; j < ents - 1; j++) {
				regs[j].phys_addr =
					regs[j+1].phys_addr;
				regs[j].reg_size =
					regs[j+1].reg_size;
			}

			ents--;
			i--;
		}
	}

	*num_ents = ents;

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	sort(regs, ents, sizeof(struct linux_prom64_registers),
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	     cmp_p64, NULL);
}
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unsigned long *sparc64_valid_addr_bitmap __read_mostly;
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/* Kernel physical address base and size in bytes.  */
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unsigned long kern_base __read_mostly;
unsigned long kern_size __read_mostly;
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/* get_new_mmu_context() uses "cache + 1".  */
DEFINE_SPINLOCK(ctx_alloc_lock);
unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];

/* References to special section boundaries */
extern char  _start[], _end[];

/* Initial ramdisk setup */
extern unsigned long sparc_ramdisk_image64;
extern unsigned int sparc_ramdisk_image;
extern unsigned int sparc_ramdisk_size;

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struct page *mem_map_zero __read_mostly;
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unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;

unsigned long sparc64_kern_pri_context __read_mostly;
unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
unsigned long sparc64_kern_sec_context __read_mostly;

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int bigkernel = 0;

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struct kmem_cache *pgtable_cache __read_mostly;
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static void zero_ctor(void *addr, struct kmem_cache *cache, unsigned long flags)
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{
	clear_page(addr);
}
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extern void tsb_cache_init(void);

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void pgtable_cache_init(void)
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{
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	pgtable_cache = kmem_cache_create("pgtable_cache",
					  PAGE_SIZE, PAGE_SIZE,
					  SLAB_HWCACHE_ALIGN |
					  SLAB_MUST_HWCACHE_ALIGN,
					  zero_ctor,
					  NULL);
	if (!pgtable_cache) {
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		prom_printf("Could not create pgtable_cache\n");
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		prom_halt();
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	}
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	tsb_cache_init();
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}

#ifdef CONFIG_DEBUG_DCFLUSH
atomic_t dcpage_flushes = ATOMIC_INIT(0);
#ifdef CONFIG_SMP
atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
#endif
#endif

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inline void flush_dcache_page_impl(struct page *page)
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{
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	BUG_ON(tlb_type == hypervisor);
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#ifdef CONFIG_DEBUG_DCFLUSH
	atomic_inc(&dcpage_flushes);
#endif

#ifdef DCACHE_ALIASING_POSSIBLE
	__flush_dcache_page(page_address(page),
			    ((tlb_type == spitfire) &&
			     page_mapping(page) != NULL));
#else
	if (page_mapping(page) != NULL &&
	    tlb_type == spitfire)
		__flush_icache_page(__pa(page_address(page)));
#endif
}

#define PG_dcache_dirty		PG_arch_1
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#define PG_dcache_cpu_shift	24UL
#define PG_dcache_cpu_mask	(256UL - 1UL)
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#if NR_CPUS > 256
#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
#endif
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#define dcache_dirty_cpu(page) \
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	(((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
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static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
{
	unsigned long mask = this_cpu;
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	unsigned long non_cpu_bits;

	non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
	mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);

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	__asm__ __volatile__("1:\n\t"
			     "ldx	[%2], %%g7\n\t"
			     "and	%%g7, %1, %%g1\n\t"
			     "or	%%g1, %0, %%g1\n\t"
			     "casx	[%2], %%g7, %%g1\n\t"
			     "cmp	%%g7, %%g1\n\t"
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			     "membar	#StoreLoad | #StoreStore\n\t"
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			     "bne,pn	%%xcc, 1b\n\t"
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			     " nop"
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			     : /* no outputs */
			     : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
			     : "g1", "g7");
}

static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
{
	unsigned long mask = (1UL << PG_dcache_dirty);

	__asm__ __volatile__("! test_and_clear_dcache_dirty\n"
			     "1:\n\t"
			     "ldx	[%2], %%g7\n\t"
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			     "srlx	%%g7, %4, %%g1\n\t"
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			     "and	%%g1, %3, %%g1\n\t"
			     "cmp	%%g1, %0\n\t"
			     "bne,pn	%%icc, 2f\n\t"
			     " andn	%%g7, %1, %%g1\n\t"
			     "casx	[%2], %%g7, %%g1\n\t"
			     "cmp	%%g7, %%g1\n\t"
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			     "membar	#StoreLoad | #StoreStore\n\t"
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			     "bne,pn	%%xcc, 1b\n\t"
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			     " nop\n"
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			     "2:"
			     : /* no outputs */
			     : "r" (cpu), "r" (mask), "r" (&page->flags),
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			       "i" (PG_dcache_cpu_mask),
			       "i" (PG_dcache_cpu_shift)
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			     : "g1", "g7");
}

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static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
{
	unsigned long tsb_addr = (unsigned long) ent;

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	if (tlb_type == cheetah_plus || tlb_type == hypervisor)
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		tsb_addr = __pa(tsb_addr);

	__tsb_insert(tsb_addr, tag, pte);
}

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unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
unsigned long _PAGE_SZBITS __read_mostly;

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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
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	struct mm_struct *mm;
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	struct tsb *tsb;
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	unsigned long tag, flags;
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	unsigned long tsb_index, tsb_hash_shift;
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	if (tlb_type != hypervisor) {
		unsigned long pfn = pte_pfn(pte);
		unsigned long pg_flags;
		struct page *page;

		if (pfn_valid(pfn) &&
		    (page = pfn_to_page(pfn), page_mapping(page)) &&
		    ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
			int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
				   PG_dcache_cpu_mask);
			int this_cpu = get_cpu();

			/* This is just to optimize away some function calls
			 * in the SMP case.
			 */
			if (cpu == this_cpu)
				flush_dcache_page_impl(page);
			else
				smp_flush_dcache_page_impl(page, cpu);

			clear_dcache_dirty_cpu(page, cpu);

			put_cpu();
		}
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	}
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	mm = vma->vm_mm;
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	tsb_index = MM_TSB_BASE;
	tsb_hash_shift = PAGE_SHIFT;

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	spin_lock_irqsave(&mm->context.lock, flags);

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#ifdef CONFIG_HUGETLB_PAGE
	if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
		if ((tlb_type == hypervisor &&
		     (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
		    (tlb_type != hypervisor &&
		     (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
			tsb_index = MM_TSB_HUGE;
			tsb_hash_shift = HPAGE_SHIFT;
		}
	}
#endif

	tsb = mm->context.tsb_block[tsb_index].tsb;
	tsb += ((address >> tsb_hash_shift) &
		(mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
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	tag = (address >> 22UL);
	tsb_insert(tsb, tag, pte_val(pte));
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	spin_unlock_irqrestore(&mm->context.lock, flags);
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}

void flush_dcache_page(struct page *page)
{
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	struct address_space *mapping;
	int this_cpu;
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	if (tlb_type == hypervisor)
		return;

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	/* Do not bother with the expensive D-cache flush if it
	 * is merely the zero page.  The 'bigcore' testcase in GDB
	 * causes this case to run millions of times.
	 */
	if (page == ZERO_PAGE(0))
		return;

	this_cpu = get_cpu();

	mapping = page_mapping(page);
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	if (mapping && !mapping_mapped(mapping)) {
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		int dirty = test_bit(PG_dcache_dirty, &page->flags);
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		if (dirty) {
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			int dirty_cpu = dcache_dirty_cpu(page);

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			if (dirty_cpu == this_cpu)
				goto out;
			smp_flush_dcache_page_impl(page, dirty_cpu);
		}
		set_dcache_dirty(page, this_cpu);
	} else {
		/* We could delay the flush for the !page_mapping
		 * case too.  But that case is for exec env/arg
		 * pages and those are %99 certainly going to get
		 * faulted into the tlb (and thus flushed) anyways.
		 */
		flush_dcache_page_impl(page);
	}

out:
	put_cpu();
}

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void __kprobes flush_icache_range(unsigned long start, unsigned long end)
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{
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	/* Cheetah and Hypervisor platform cpus have coherent I-cache. */
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	if (tlb_type == spitfire) {
		unsigned long kaddr;

		for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
			__flush_icache_page(__get_phys(kaddr));
	}
}

void show_mem(void)
{
	printk("Mem-info:\n");
	show_free_areas();
	printk("Free swap:       %6ldkB\n",
	       nr_swap_pages << (PAGE_SHIFT-10));
	printk("%ld pages of RAM\n", num_physpages);
	printk("%d free pages\n", nr_free_pages());
}

void mmu_info(struct seq_file *m)
{
	if (tlb_type == cheetah)
		seq_printf(m, "MMU Type\t: Cheetah\n");
	else if (tlb_type == cheetah_plus)
		seq_printf(m, "MMU Type\t: Cheetah+\n");
	else if (tlb_type == spitfire)
		seq_printf(m, "MMU Type\t: Spitfire\n");
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	else if (tlb_type == hypervisor)
		seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
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	else
		seq_printf(m, "MMU Type\t: ???\n");

#ifdef CONFIG_DEBUG_DCFLUSH
	seq_printf(m, "DCPageFlushes\t: %d\n",
		   atomic_read(&dcpage_flushes));
#ifdef CONFIG_SMP
	seq_printf(m, "DCPageFlushesXC\t: %d\n",
		   atomic_read(&dcpage_flushes_xcall));
#endif /* CONFIG_SMP */
#endif /* CONFIG_DEBUG_DCFLUSH */
}

struct linux_prom_translation {
	unsigned long virt;
	unsigned long size;
	unsigned long data;
};
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/* Exported for kernel TLB miss handling in ktlb.S */
struct linux_prom_translation prom_trans[512] __read_mostly;
unsigned int prom_trans_ents __read_mostly;
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/* Exported for SMP bootup purposes. */
unsigned long kern_locked_tte_data;

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/* The obp translations are saved based on 8k pagesize, since obp can
 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
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 * HI_OBP_ADDRESS range are handled in ktlb.S.
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 */
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static inline int in_obp_range(unsigned long vaddr)
{
	return (vaddr >= LOW_OBP_ADDRESS &&
		vaddr < HI_OBP_ADDRESS);
}

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static int cmp_ptrans(const void *a, const void *b)
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{
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	const struct linux_prom_translation *x = a, *y = b;
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	if (x->virt > y->virt)
		return 1;
	if (x->virt < y->virt)
		return -1;
	return 0;
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}

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/* Read OBP translations property into 'prom_trans[]'.  */
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static void __init read_obp_translations(void)
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{
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	int n, node, ents, first, last, i;
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	node = prom_finddevice("/virtual-memory");
	n = prom_getproplen(node, "translations");
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	if (unlikely(n == 0 || n == -1)) {
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		prom_printf("prom_mappings: Couldn't get size.\n");
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		prom_halt();
	}
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	if (unlikely(n > sizeof(prom_trans))) {
		prom_printf("prom_mappings: Size %Zd is too big.\n", n);
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		prom_halt();
	}
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	if ((n = prom_getproperty(node, "translations",
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				  (char *)&prom_trans[0],
				  sizeof(prom_trans))) == -1) {
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		prom_printf("prom_mappings: Couldn't get property.\n");
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		prom_halt();
	}
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	n = n / sizeof(struct linux_prom_translation);
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	ents = n;

	sort(prom_trans, ents, sizeof(struct linux_prom_translation),
	     cmp_ptrans, NULL);

	/* Now kick out all the non-OBP entries.  */
	for (i = 0; i < ents; i++) {
		if (in_obp_range(prom_trans[i].virt))
			break;
	}
	first = i;
	for (; i < ents; i++) {
		if (!in_obp_range(prom_trans[i].virt))
			break;
	}
	last = i;

	for (i = 0; i < (last - first); i++) {
		struct linux_prom_translation *src = &prom_trans[i + first];
		struct linux_prom_translation *dest = &prom_trans[i];

		*dest = *src;
	}
	for (; i < ents; i++) {
		struct linux_prom_translation *dest = &prom_trans[i];
		dest->virt = dest->size = dest->data = 0x0UL;
	}

	prom_trans_ents = last - first;

	if (tlb_type == spitfire) {
		/* Clear diag TTE bits. */
		for (i = 0; i < prom_trans_ents; i++)
			prom_trans[i].data &= ~0x0003fe0000000000UL;
	}
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}
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static void __init hypervisor_tlb_lock(unsigned long vaddr,
				       unsigned long pte,
				       unsigned long mmu)
{
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	register unsigned long func asm("%o5");
	register unsigned long arg0 asm("%o0");
	register unsigned long arg1 asm("%o1");
	register unsigned long arg2 asm("%o2");
	register unsigned long arg3 asm("%o3");
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	func = HV_FAST_MMU_MAP_PERM_ADDR;
	arg0 = vaddr;
	arg1 = 0;
	arg2 = pte;
	arg3 = mmu;
	__asm__ __volatile__("ta	0x80"
			     : "=&r" (func), "=&r" (arg0),
			       "=&r" (arg1), "=&r" (arg2),
			       "=&r" (arg3)
			     : "0" (func), "1" (arg0), "2" (arg1),
			       "3" (arg2), "4" (arg3));
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	if (arg0 != 0) {
		prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
			    "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
		prom_halt();
	}
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}

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static unsigned long kern_large_tte(unsigned long paddr);

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static void __init remap_kernel(void)
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{
	unsigned long phys_page, tte_vaddr, tte_data;
	int tlb_ent = sparc64_highest_locked_tlbent();

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	tte_vaddr = (unsigned long) KERNBASE;
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	phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
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	tte_data = kern_large_tte(phys_page);
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	kern_locked_tte_data = tte_data;

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	/* Now lock us into the TLBs via Hypervisor or OBP. */
	if (tlb_type == hypervisor) {
		hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
		hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
		if (bigkernel) {
			tte_vaddr += 0x400000;
			tte_data += 0x400000;
			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
		}
	} else {
		prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
		prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
		if (bigkernel) {
			tlb_ent -= 1;
			prom_dtlb_load(tlb_ent,
				       tte_data + 0x400000, 
				       tte_vaddr + 0x400000);
			prom_itlb_load(tlb_ent,
				       tte_data + 0x400000, 
				       tte_vaddr + 0x400000);
		}
		sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
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	}
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	if (tlb_type == cheetah_plus) {
		sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
					    CTX_CHEETAH_PLUS_NUC);
		sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
		sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
	}
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}
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static void __init inherit_prom_mappings(void)
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{
	read_obp_translations();
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	/* Now fixup OBP's idea about where we really are mapped. */
	prom_printf("Remapping the kernel... ");
	remap_kernel();
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	prom_printf("done.\n");
}

void prom_world(int enter)
{
	if (!enter)
		set_fs((mm_segment_t) { get_thread_current_ds() });

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	__asm__ __volatile__("flushw");
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}

#ifdef DCACHE_ALIASING_POSSIBLE
void __flush_dcache_range(unsigned long start, unsigned long end)
{
	unsigned long va;

	if (tlb_type == spitfire) {
		int n = 0;

		for (va = start; va < end; va += 32) {
			spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
			if (++n >= 512)
				break;
		}
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	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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		start = __pa(start);
		end = __pa(end);
		for (va = start; va < end; va += 32)
			__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
					     "membar #Sync"
					     : /* no outputs */
					     : "r" (va),
					       "i" (ASI_DCACHE_INVALIDATE));
	}
}
#endif /* DCACHE_ALIASING_POSSIBLE */

/* Caller does TLB context flushing on local CPU if necessary.
 * The caller also ensures that CTX_VALID(mm->context) is false.
 *
 * We must be careful about boundary cases so that we never
 * let the user have CTX 0 (nucleus) or we ever use a CTX
 * version of zero (and thus NO_CONTEXT would not be caught
 * by version mis-match tests in mmu_context.h).
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 *
 * Always invoked with interrupts disabled.
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 */
void get_new_mmu_context(struct mm_struct *mm)
{
	unsigned long ctx, new_ctx;
	unsigned long orig_pgsz_bits;
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	unsigned long flags;
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	int new_version;
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	spin_lock_irqsave(&ctx_alloc_lock, flags);
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	orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
	ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
	new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
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	new_version = 0;
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	if (new_ctx >= (1 << CTX_NR_BITS)) {
		new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
		if (new_ctx >= ctx) {
			int i;
			new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
				CTX_FIRST_VERSION;
			if (new_ctx == 1)
				new_ctx = CTX_FIRST_VERSION;

			/* Don't call memset, for 16 entries that's just
			 * plain silly...
			 */
			mmu_context_bmap[0] = 3;
			mmu_context_bmap[1] = 0;
			mmu_context_bmap[2] = 0;
			mmu_context_bmap[3] = 0;
			for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
				mmu_context_bmap[i + 0] = 0;
				mmu_context_bmap[i + 1] = 0;
				mmu_context_bmap[i + 2] = 0;
				mmu_context_bmap[i + 3] = 0;
			}
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			new_version = 1;
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			goto out;
		}
	}
	mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
	new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
out:
	tlb_context_cache = new_ctx;
	mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
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	spin_unlock_irqrestore(&ctx_alloc_lock, flags);
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	if (unlikely(new_version))
		smp_new_mmu_context_version();
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}

void sparc_ultra_dump_itlb(void)
{
        int slot;

	if (tlb_type == spitfire) {
		printk ("Contents of itlb: ");
		for (slot = 0; slot < 14; slot++) printk ("    ");
		printk ("%2x:%016lx,%016lx\n",
			0,
			spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
		for (slot = 1; slot < 64; slot+=3) {
			printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
				slot,
				spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
				slot+1,
				spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
				slot+2,
				spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
		}
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		printk ("Contents of itlb0:\n");
		for (slot = 0; slot < 16; slot+=2) {
			printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
				slot,
				cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
				slot+1,
				cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
		}
		printk ("Contents of itlb2:\n");
		for (slot = 0; slot < 128; slot+=2) {
			printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
				slot,
				cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
				slot+1,
				cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
		}
	}
}

void sparc_ultra_dump_dtlb(void)
{
        int slot;

	if (tlb_type == spitfire) {
		printk ("Contents of dtlb: ");
		for (slot = 0; slot < 14; slot++) printk ("    ");
		printk ("%2x:%016lx,%016lx\n", 0,
			spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
		for (slot = 1; slot < 64; slot+=3) {
			printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
				slot,
				spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
				slot+1,
				spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
				slot+2,
				spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
		}
	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
		printk ("Contents of dtlb0:\n");
		for (slot = 0; slot < 16; slot+=2) {
			printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
				slot,
				cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
				slot+1,
				cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
		}
		printk ("Contents of dtlb2:\n");
		for (slot = 0; slot < 512; slot+=2) {
			printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
				slot,
				cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
				slot+1,
				cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
		}
		if (tlb_type == cheetah_plus) {
			printk ("Contents of dtlb3:\n");
			for (slot = 0; slot < 512; slot+=2) {
				printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
					slot,
					cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
					slot+1,
					cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
			}
		}
	}
}

extern unsigned long cmdline_memory_size;

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/* Find a free area for the bootmem map, avoiding the kernel image
 * and the initial ramdisk.
 */
static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
					       unsigned long end_pfn)
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{
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	unsigned long avoid_start, avoid_end, bootmap_size;
	int i;

	bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
	bootmap_size = ALIGN(bootmap_size, sizeof(long));

	avoid_start = avoid_end = 0;
#ifdef CONFIG_BLK_DEV_INITRD
	avoid_start = initrd_start;
	avoid_end = PAGE_ALIGN(initrd_end);
#endif

#ifdef CONFIG_DEBUG_BOOTMEM
	prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
		    kern_base, PAGE_ALIGN(kern_base + kern_size),
		    avoid_start, avoid_end);
#endif
	for (i = 0; i < pavail_ents; i++) {
		unsigned long start, end;

		start = pavail[i].phys_addr;
		end = start + pavail[i].reg_size;

		while (start < end) {
			if (start >= kern_base &&
			    start < PAGE_ALIGN(kern_base + kern_size)) {
				start = PAGE_ALIGN(kern_base + kern_size);
				continue;
			}
			if (start >= avoid_start && start < avoid_end) {
				start = avoid_end;
				continue;
			}

			if ((end - start) < bootmap_size)
				break;

			if (start < kern_base &&
			    (start + bootmap_size) > kern_base) {
				start = PAGE_ALIGN(kern_base + kern_size);
				continue;
			}

			if (start < avoid_start &&
			    (start + bootmap_size) > avoid_start) {
				start = avoid_end;
				continue;
			}

			/* OK, it doesn't overlap anything, use it.  */
#ifdef CONFIG_DEBUG_BOOTMEM
			prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
				    start >> PAGE_SHIFT, start);
#endif
			return start >> PAGE_SHIFT;
		}
	}

	prom_printf("Cannot find free area for bootmap, aborting.\n");
	prom_halt();
}

static unsigned long __init bootmem_init(unsigned long *pages_avail,
					 unsigned long phys_base)
{
	unsigned long bootmap_size, end_pfn;
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	unsigned long end_of_phys_memory = 0UL;
	unsigned long bootmap_pfn, bytes_avail, size;
	int i;

#ifdef CONFIG_DEBUG_BOOTMEM
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	prom_printf("bootmem_init: Scan pavail, ");
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#endif

	bytes_avail = 0UL;
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	for (i = 0; i < pavail_ents; i++) {
		end_of_phys_memory = pavail[i].phys_addr +
			pavail[i].reg_size;
		bytes_avail += pavail[i].reg_size;
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		if (cmdline_memory_size) {
			if (bytes_avail > cmdline_memory_size) {
				unsigned long slack = bytes_avail - cmdline_memory_size;

				bytes_avail -= slack;
				end_of_phys_memory -= slack;

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				pavail[i].reg_size -= slack;
				if ((long)pavail[i].reg_size <= 0L) {
					pavail[i].phys_addr = 0xdeadbeefUL;
					pavail[i].reg_size = 0UL;
					pavail_ents = i;
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				} else {
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					pavail[i+1].reg_size = 0Ul;
					pavail[i+1].phys_addr = 0xdeadbeefUL;
					pavail_ents = i + 1;
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				}
				break;
			}
		}
	}

	*pages_avail = bytes_avail >> PAGE_SHIFT;

	end_pfn = end_of_phys_memory >> PAGE_SHIFT;

#ifdef CONFIG_BLK_DEV_INITRD
	/* Now have to check initial ramdisk, so that bootmap does not overwrite it */
	if (sparc_ramdisk_image || sparc_ramdisk_image64) {
		unsigned long ramdisk_image = sparc_ramdisk_image ?
			sparc_ramdisk_image : sparc_ramdisk_image64;
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		ramdisk_image -= KERNBASE;
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		initrd_start = ramdisk_image + phys_base;
		initrd_end = initrd_start + sparc_ramdisk_size;
		if (initrd_end > end_of_phys_memory) {
			printk(KERN_CRIT "initrd extends beyond end of memory "
		                 	 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
			       initrd_end, end_of_phys_memory);
			initrd_start = 0;
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			initrd_end = 0;
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		}
	}
#endif	
	/* Initialize the boot-time allocator. */
	max_pfn = max_low_pfn = end_pfn;
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	min_low_pfn = (phys_base >> PAGE_SHIFT);

	bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
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#ifdef CONFIG_DEBUG_BOOTMEM
	prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
		    min_low_pfn, bootmap_pfn, max_low_pfn);
#endif
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	bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
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					 min_low_pfn, end_pfn);
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	/* Now register the available physical memory with the
	 * allocator.
	 */
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	for (i = 0; i < pavail_ents; i++) {
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#ifdef CONFIG_DEBUG_BOOTMEM
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		prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
			    i, pavail[i].phys_addr, pavail[i].reg_size);
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#endif
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		free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
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	}

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start) {
		size = initrd_end - initrd_start;

		/* Resert the initrd image area. */
#ifdef CONFIG_DEBUG_BOOTMEM
		prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
			initrd_start, initrd_end);
#endif
		reserve_bootmem(initrd_start, size);
		*pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;

		initrd_start += PAGE_OFFSET;
		initrd_end += PAGE_OFFSET;
	}
#endif
	/* Reserve the kernel text/data/bss. */
#ifdef CONFIG_DEBUG_BOOTMEM
	prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
#endif
	reserve_bootmem(kern_base, kern_size);
	*pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;

	/* Reserve the bootmem map.   We do not account for it
	 * in pages_avail because we will release that memory
	 * in free_all_bootmem.
	 */
	size = bootmap_size;
#ifdef CONFIG_DEBUG_BOOTMEM
	prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
		    (bootmap_pfn << PAGE_SHIFT), size);
#endif
	reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
	*pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;

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	for (i = 0; i < pavail_ents; i++) {
		unsigned long start_pfn, end_pfn;

		start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
		end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
#ifdef CONFIG_DEBUG_BOOTMEM
		prom_printf("memory_present(0, %lx, %lx)\n",
			    start_pfn, end_pfn);
#endif
		memory_present(0, start_pfn, end_pfn);
	}

	sparse_init();

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	return end_pfn;
}

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static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
static int pall_ents __initdata;

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#ifdef CONFIG_DEBUG_PAGEALLOC
static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
{
	unsigned long vstart = PAGE_OFFSET + pstart;
	unsigned long vend = PAGE_OFFSET + pend;
	unsigned long alloc_bytes = 0UL;

	if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
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		prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
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			    vstart, vend);
		prom_halt();
	}

	while (vstart < vend) {
		unsigned long this_end, paddr = __pa(vstart);
		pgd_t *pgd = pgd_offset_k(vstart);
		pud_t *pud;
		pmd_t *pmd;
		pte_t *pte;

		pud = pud_offset(pgd, vstart);
		if (pud_none(*pud)) {
			pmd_t *new;

			new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
			alloc_bytes += PAGE_SIZE;
			pud_populate(&init_mm, pud, new);
		}

		pmd = pmd_offset(pud, vstart);
		if (!pmd_present(*pmd)) {
			pte_t *new;

			new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
			alloc_bytes += PAGE_SIZE;
			pmd_populate_kernel(&init_mm, pmd, new);
		}

		pte = pte_offset_kernel(pmd, vstart);
		this_end = (vstart + PMD_SIZE) & PMD_MASK;
		if (this_end > vend)
			this_end = vend;

		while (vstart < this_end) {
			pte_val(*pte) = (paddr | pgprot_val(prot));

			vstart += PAGE_SIZE;
			paddr += PAGE_SIZE;
			pte++;
		}
	}

	return alloc_bytes;
}

extern unsigned int kvmap_linear_patch[1];
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#endif /* CONFIG_DEBUG_PAGEALLOC */

static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
{
	const unsigned long shift_256MB = 28;
	const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
	const unsigned long size_256MB = (1UL << shift_256MB);

	while (start < end) {
		long remains;

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		remains = end - start;
		if (remains < size_256MB)
			break;

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		if (start & mask_256MB) {
			start = (start + size_256MB) & ~mask_256MB;
			continue;
		}

		while (remains >= size_256MB) {
			unsigned long index = start >> shift_256MB;

			__set_bit(index, kpte_linear_bitmap);

			start += size_256MB;
			remains -= size_256MB;
		}
	}
}
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static void __init kernel_physical_mapping_init(void)
{
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	unsigned long i;
#ifdef CONFIG_DEBUG_PAGEALLOC
	unsigned long mem_alloced = 0UL;
#endif
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	read_obp_memory("reg", &pall[0], &pall_ents);

	for (i = 0; i < pall_ents; i++) {
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		unsigned long phys_start, phys_end;

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		phys_start = pall[i].phys_addr;
		phys_end = phys_start + pall[i].reg_size;
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		mark_kpte_bitmap(phys_start, phys_end);

#ifdef CONFIG_DEBUG_PAGEALLOC
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		mem_alloced += kernel_map_range(phys_start, phys_end,
						PAGE_KERNEL);
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#endif
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	}

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#ifdef CONFIG_DEBUG_PAGEALLOC
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	printk("Allocated %ld bytes for kernel page tables.\n",
	       mem_alloced);

	kvmap_linear_patch[0] = 0x01000000; /* nop */
	flushi(&kvmap_linear_patch[0]);

	__flush_tlb_all();
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#endif
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}

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#ifdef CONFIG_DEBUG_PAGEALLOC
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void kernel_map_pages(struct page *page, int numpages, int enable)
{
	unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
	unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);

	kernel_map_range(phys_start, phys_end,
			 (enable ? PAGE_KERNEL : __pgprot(0)));

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	flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
			       PAGE_OFFSET + phys_end);

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	/* we should perform an IPI and flush all tlbs,
	 * but that can deadlock->flush only current cpu.
	 */
	__flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
				 PAGE_OFFSET + phys_end);
}
#endif

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unsigned long __init find_ecache_flush_span(unsigned long size)
{
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	int i;

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	for (i = 0; i < pavail_ents; i++) {
		if (pavail[i].reg_size >= size)
			return pavail[i].phys_addr;
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	}

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	return ~0UL;
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}

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static void __init tsb_phys_patch(void)
{
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	struct tsb_ldquad_phys_patch_entry *pquad;
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	struct tsb_phys_patch_entry *p;

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	pquad = &__tsb_ldquad_phys_patch;
	while (pquad < &__tsb_ldquad_phys_patch_end) {
		unsigned long addr = pquad->addr;

		if (tlb_type == hypervisor)
			*(unsigned int *) addr = pquad->sun4v_insn;
		else
			*(unsigned int *) addr = pquad->sun4u_insn;
		wmb();
		__asm__ __volatile__("flush	%0"
				     : /* no outputs */
				     : "r" (addr));

		pquad++;
	}

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	p = &__tsb_phys_patch;
	while (p < &__tsb_phys_patch_end) {
		unsigned long addr = p->addr;

		*(unsigned int *) addr = p->insn;
		wmb();
		__asm__ __volatile__("flush	%0"
				     : /* no outputs */
				     : "r" (addr));

		p++;
	}
}

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/* Don't mark as init, we give this to the Hypervisor.  */
static struct hv_tsb_descr ktsb_descr[2];
extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];

static void __init sun4v_ktsb_init(void)
{
	unsigned long ktsb_pa;

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	/* First KTSB for PAGE_SIZE mappings.  */
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	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);

	switch (PAGE_SIZE) {
	case 8 * 1024:
	default:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
		break;

	case 64 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
		break;

	case 512 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
		break;

	case 4 * 1024 * 1024:
		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
		break;
	};

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	ktsb_descr[0].assoc = 1;
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	ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
	ktsb_descr[0].ctx_idx = 0;
	ktsb_descr[0].tsb_base = ktsb_pa;
	ktsb_descr[0].resv = 0;

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	/* Second KTSB for 4MB/256MB mappings.  */
	ktsb_pa = (kern_base +
		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));

	ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
	ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
				   HV_PGSZ_MASK_256MB);
	ktsb_descr[1].assoc = 1;
	ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
	ktsb_descr[1].ctx_idx = 0;
	ktsb_descr[1].tsb_base = ktsb_pa;
	ktsb_descr[1].resv = 0;
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}

void __cpuinit sun4v_ktsb_register(void)
{
	register unsigned long func asm("%o5");
	register unsigned long arg0 asm("%o0");
	register unsigned long arg1 asm("%o1");
	unsigned long pa;

	pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);

	func = HV_FAST_MMU_TSB_CTX0;
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	arg0 = 2;
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	arg1 = pa;
	__asm__ __volatile__("ta	%6"
			     : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
			     : "0" (func), "1" (arg0), "2" (arg1),
			       "i" (HV_FAST_TRAP));
}

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/* paging_init() sets up the page tables */

extern void cheetah_ecache_flush_init(void);
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extern void sun4v_patch_tlb_handlers(void);
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static unsigned long last_valid_pfn;
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pgd_t swapper_pg_dir[2048];
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static void sun4u_pgprot_init(void);
static void sun4v_pgprot_init(void);

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void __init paging_init(void)
{
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	unsigned long end_pfn, pages_avail, shift, phys_base;
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	unsigned long real_end, i;

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	kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
	kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;

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	/* Invalidate both kernel TSBs.  */
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	memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
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	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
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	if (tlb_type == hypervisor)
		sun4v_pgprot_init();
	else
		sun4u_pgprot_init();

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	if (tlb_type == cheetah_plus ||
	    tlb_type == hypervisor)
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		tsb_phys_patch();

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	if (tlb_type == hypervisor) {
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		sun4v_patch_tlb_handlers();
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		sun4v_ktsb_init();
	}
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	/* Find available physical memory... */
	read_obp_memory("available", &pavail[0], &pavail_ents);
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	phys_base = 0xffffffffffffffffUL;