LS1088A contains eight ARM v8 CortexA53 processor cores
with 32 KB L1-D cache and 32 KB L1-I cache

Features summary
 Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
  - Arranged as two clusters of four cores sharing a 1 MB L2 cache
  - Speed Up to 1.5 GHz
  - Support for cluster power-gating.
 Cache coherent interconnect (CCI-400)
  - Hardware-managed data coherency
  - Up to 700 MHz
 One 64-bit DDR4 SDRAM memory controller with ECC
 Data path acceleration architecture 2.0 (DPAA2)
 Three PCIe 3.0 controllers
 One serial ATA (SATA 3.0) controller
 Three high-speed USB 3.0 controllers with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1088A
  SoC family:

         - fsl-ls1088a.dtsi:
                 DTS-Include file for NXP LS1088A SoC.

         - fsl-ls1088a-qds.dts:
                 DTS file for NXP LS1088A QDS board.

         - fsl-ls1088a-rdb.dts:
                 DTS file for NXP LS1088A RDB board

Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com&gt;`>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>