Merge branch 'f/4.18/emmc' into imx8-4.18-wip

arch/arm64/boot/dts/freescale/imx8mq.dtsi

@@ -1085,6 +1085,7 @@
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step = <2>;
+				fsl,strobe-dll-delay-target = <5>;
 				bus-width = <4>;
 				status = "disabled";
 			};

arch/arm64/boot/dts/freescale/librem5-evk.dts

@@ -426,34 +426,34 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
-				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
-				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
-				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
-				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
-				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
-				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
-				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
-				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
-				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
-				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
 				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
 			>;
 		};
@@ -478,23 +478,23 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
-				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
-				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
-				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
-				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcf
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcf
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcf
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcf
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcf
 			>;
 		};