- 14 Dec, 2018 2 commits
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
The one we're keeping up to date is emcraft-imx8-som.dts for emcrafts imx8 som evk. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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- 13 Dec, 2018 3 commits
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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- 12 Dec, 2018 8 commits
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
As the typec port controller interface(TCPCI) spec requires the i2c clock at least to be 400K, so here increase it to be 400K to meet timing requirement. Acked-by:
Peter Chen <peter.chen@nxp.com> Signed-off-by:
Li Jun <jun.li@nxp.com>
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
On some i.MX8MQ-EVK A0/A1 board, we may meet eMMC read data CRC error in HS400 mode. This is because the delay cell set for the strobe pad is not correct. Before this patch, usdhc driver default set this delay cell to value 7, but for some board, only value 3~6 can pass read operation in HS400 mode, some board, the pass value is 2~10, and some board, the pass value is 3~8. So the default value 7 can't make sure all the board can pass eMMC read in HS400. This patch set the value 5 to fsl,strobe-dll-delay-target, make sure all the board can work stable in HS400 mode. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com>
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Angus Ainslie (Purism) authored
According to RM, usdhc 100MHz pad setting need to set SRE(slew rate field) to 0x01(Medium Frequency Slew Rate 100MHz), usdhc 200MHz pad setting need to set SRE to 0x11(Max Frequency Slew Rate 200MHz). Without this patch, eMMC HS400 will meet timeout/crc error when the temperature is over 80 degree celsius. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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- 10 Nov, 2018 3 commits
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Guido Gunther authored
Don't make the bridge handle this. This allows us to respect the panel's reset specifics. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
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- 03 Nov, 2018 3 commits
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Angus Ainslie authored
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Angus Ainslie authored
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Angus Ainslie authored
On i.MX8MQ, when the CPU core is in power down state, the IPI can NOT wakeup the core anymore(ERR011171), so using the external IRQ32 to wakeup the core in power down idle state successfully. Signed-off-by:
Bai Ping <ping.bai@nxp.com> Reviewed-by:
Anson Huang <anson.huang@nxp.com>
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- 29 Oct, 2018 3 commits
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Angus Ainslie (Purism) authored
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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- 25 Oct, 2018 1 commit
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Angus Ainslie (Purism) authored
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- 24 Oct, 2018 2 commits
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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- 23 Oct, 2018 3 commits
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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- 21 Oct, 2018 1 commit
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Angus Ainslie (Purism) authored
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- 20 Oct, 2018 1 commit
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Angus Ainslie (Purism) authored
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- 19 Oct, 2018 10 commits
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Guido Günther via Librem-5-dev authored
Since related also drop unneeded flags from the pwm1's pin definition.
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
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