dmaengine.h 46.1 KB
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/*
 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
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#ifndef LINUX_DMAENGINE_H
#define LINUX_DMAENGINE_H
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/uio.h>
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#include <linux/bug.h>
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#include <linux/scatterlist.h>
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <asm/page.h>
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/**
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 * typedef dma_cookie_t - an opaque DMA cookie
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 *
 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 */
typedef s32 dma_cookie_t;
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#define DMA_MIN_COOKIE	1
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static inline int dma_submit_error(dma_cookie_t cookie)
{
	return cookie < 0 ? cookie : 0;
}
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/**
 * enum dma_status - DMA transaction status
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 * @DMA_COMPLETE: transaction completed
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 * @DMA_IN_PROGRESS: transaction not yet processed
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 * @DMA_PAUSED: transaction is paused
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 * @DMA_ERROR: transaction failed
 */
enum dma_status {
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	DMA_COMPLETE,
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	DMA_IN_PROGRESS,
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	DMA_PAUSED,
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	DMA_ERROR,
};

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/**
 * enum dma_transaction_type - DMA transaction types/indexes
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 *
 * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 * automatically set as dma devices are registered.
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 */
enum dma_transaction_type {
	DMA_MEMCPY,
	DMA_XOR,
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	DMA_PQ,
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	DMA_XOR_VAL,
	DMA_PQ_VAL,
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	DMA_MEMSET,
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	DMA_MEMSET_SG,
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	DMA_INTERRUPT,
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	DMA_SG,
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	DMA_PRIVATE,
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	DMA_ASYNC_TX,
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	DMA_SLAVE,
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	DMA_CYCLIC,
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	DMA_INTERLEAVE,
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/* last transaction type for creation of the capabilities mask */
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	DMA_TX_TYPE_END,
};
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/**
 * enum dma_transfer_direction - dma transfer mode and direction indicator
 * @DMA_MEM_TO_MEM: Async/Memcpy mode
 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 */
enum dma_transfer_direction {
	DMA_MEM_TO_MEM,
	DMA_MEM_TO_DEV,
	DMA_DEV_TO_MEM,
	DMA_DEV_TO_DEV,
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	DMA_TRANS_NONE,
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};
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/**
 * Interleaved Transfer Request
 * ----------------------------
 * A chunk is collection of contiguous bytes to be transfered.
 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
 * ICGs may or maynot change between chunks.
 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
 *  that when repeated an integral number of times, specifies the transfer.
 * A transfer template is specification of a Frame, the number of times
 *  it is to be repeated and other per-transfer attributes.
 *
 * Practically, a client driver would have ready a template for each
 *  type of transfer it is going to need during its lifetime and
 *  set only 'src_start' and 'dst_start' before submitting the requests.
 *
 *
 *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
 *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
 *
 *    ==  Chunk size
 *    ... ICG
 */

/**
 * struct data_chunk - Element of scatter-gather list that makes a frame.
 * @size: Number of bytes to read from source.
 *	  size_dst := fn(op, size_src), so doesn't mean much for destination.
 * @icg: Number of bytes to jump after last src/dst address of this
 *	 chunk and before first src/dst address for next chunk.
 *	 Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
 *	 Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
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 * @dst_icg: Number of bytes to jump after last dst address of this
 *	 chunk and before the first dst address for next chunk.
 *	 Ignored if dst_inc is true and dst_sgl is false.
 * @src_icg: Number of bytes to jump after last src address of this
 *	 chunk and before the first src address for next chunk.
 *	 Ignored if src_inc is true and src_sgl is false.
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 */
struct data_chunk {
	size_t size;
	size_t icg;
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	size_t dst_icg;
	size_t src_icg;
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};

/**
 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
 *	 and attributes.
 * @src_start: Bus address of source for the first chunk.
 * @dst_start: Bus address of destination for the first chunk.
 * @dir: Specifies the type of Source and Destination.
 * @src_inc: If the source address increments after reading from it.
 * @dst_inc: If the destination address increments after writing to it.
 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
 *		Otherwise, source is read contiguously (icg ignored).
 *		Ignored if src_inc is false.
 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
 *		Otherwise, destination is filled contiguously (icg ignored).
 *		Ignored if dst_inc is false.
 * @numf: Number of frames in this template.
 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
 * @sgl: Array of {chunk,icg} pairs that make up a frame.
 */
struct dma_interleaved_template {
	dma_addr_t src_start;
	dma_addr_t dst_start;
	enum dma_transfer_direction dir;
	bool src_inc;
	bool dst_inc;
	bool src_sgl;
	bool dst_sgl;
	size_t numf;
	size_t frame_size;
	struct data_chunk sgl[0];
};

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/**
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 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
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 *  control completion, and communicate status.
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 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
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 *  this transaction
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 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
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 *  acknowledges receipt, i.e. has has a chance to establish any dependency
 *  chains
 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
 *  sources that were the result of a previous operation, in the case of a PQ
 *  operation it continues the calculation with new sources
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 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
 *  on the result of this operation
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 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
 *  cleared or freed
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 */
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enum dma_ctrl_flags {
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	DMA_PREP_INTERRUPT = (1 << 0),
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	DMA_CTRL_ACK = (1 << 1),
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	DMA_PREP_PQ_DISABLE_P = (1 << 2),
	DMA_PREP_PQ_DISABLE_Q = (1 << 3),
	DMA_PREP_CONTINUE = (1 << 4),
	DMA_PREP_FENCE = (1 << 5),
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	DMA_CTRL_REUSE = (1 << 6),
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};

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/**
 * enum sum_check_bits - bit position of pq_check_flags
 */
enum sum_check_bits {
	SUM_CHECK_P = 0,
	SUM_CHECK_Q = 1,
};

/**
 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 */
enum sum_check_flags {
	SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
	SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
};


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/**
 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 * See linux/cpumask.h
 */
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;

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/**
 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 * @memcpy_count: transaction counter
 * @bytes_transferred: byte counter
 */

struct dma_chan_percpu {
	/* stats */
	unsigned long memcpy_count;
	unsigned long bytes_transferred;
};

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/**
 * struct dma_router - DMA router structure
 * @dev: pointer to the DMA router device
 * @route_free: function to be called when the route can be disconnected
 */
struct dma_router {
	struct device *dev;
	void (*route_free)(struct device *dev, void *route_data);
};

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/**
 * struct dma_chan - devices supply DMA channels, clients use them
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 * @device: ptr to the dma device who supplies this channel, always !%NULL
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 * @cookie: last cookie value returned to client
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 * @completed_cookie: last completed cookie for this channel
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 * @chan_id: channel ID for sysfs
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 * @dev: class device for sysfs
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 * @device_node: used to add this to the device chan list
 * @local: per-cpu pointer to a struct dma_chan_percpu
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 * @client_count: how many clients are using this channel
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 * @table_count: number of appearances in the mem-to-mem allocation table
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 * @router: pointer to the DMA router structure
 * @route_data: channel specific data for the router
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 * @private: private data for certain client-channel associations
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 */
struct dma_chan {
	struct dma_device *device;
	dma_cookie_t cookie;
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	dma_cookie_t completed_cookie;
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	/* sysfs */
	int chan_id;
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	struct dma_chan_dev *dev;
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	struct list_head device_node;
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	struct dma_chan_percpu __percpu *local;
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	int client_count;
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	int table_count;
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	/* DMA router */
	struct dma_router *router;
	void *route_data;

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	void *private;
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};

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/**
 * struct dma_chan_dev - relate sysfs device node to backing channel device
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 * @chan: driver channel device
 * @device: sysfs device
 * @dev_id: parent dma_device dev_id
 * @idr_ref: reference count to gate release of dma_device dev_id
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 */
struct dma_chan_dev {
	struct dma_chan *chan;
	struct device device;
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	int dev_id;
	atomic_t *idr_ref;
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};

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/**
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 * enum dma_slave_buswidth - defines bus width of the DMA slave
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 * device, source or target buses
 */
enum dma_slave_buswidth {
	DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
	DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
	DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
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	DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
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	DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
	DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
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	DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
	DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
	DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
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};

/**
 * struct dma_slave_config - dma slave channel runtime config
 * @direction: whether the data shall go in or out on this slave
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 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
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 * legal values. DEPRECATED, drivers should use the direction argument
 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
 * the dir field in the dma_interleaved_template structure.
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 * @src_addr: this is the physical address where DMA slave data
 * should be read (RX), if the source is memory this argument is
 * ignored.
 * @dst_addr: this is the physical address where DMA slave data
 * should be written (TX), if the source is memory this argument
 * is ignored.
 * @src_addr_width: this is the width in bytes of the source (RX)
 * register where DMA data shall be read. If the source
 * is memory this may be ignored depending on architecture.
 * Legal values: 1, 2, 4, 8.
 * @dst_addr_width: same as src_addr_width but for destination
 * target (TX) mutatis mutandis.
 * @src_maxburst: the maximum number of words (note: words, as in
 * units of the src_addr_width member, not bytes) that can be sent
 * in one burst to the device. Typically something like half the
 * FIFO depth on I/O peripherals so you don't overflow it. This
 * may or may not be applicable on memory sources.
 * @dst_maxburst: same as src_maxburst but for destination target
 * mutatis mutandis.
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 * @src_port_window_size: The length of the register area in words the data need
 * to be accessed on the device side. It is only used for devices which is using
 * an area instead of a single register to receive the data. Typically the DMA
 * loops in this area in order to transfer the data.
 * @dst_port_window_size: same as src_port_window_size but for the destination
 * port.
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 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
 * with 'true' if peripheral should be flow controller. Direction will be
 * selected at Runtime.
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 * @slave_id: Slave requester id. Only valid for slave channels. The dma
 * slave peripheral will have unique id as dma requester which need to be
 * pass as slave config.
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 *
 * This struct is passed in as configuration data to a DMA engine
 * in order to set up a certain channel for DMA transport at runtime.
 * The DMA device/engine has to provide support for an additional
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 * callback in the dma_device structure, device_config and this struct
 * will then be passed in as an argument to the function.
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 *
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 * The rationale for adding configuration information to this struct is as
 * follows: if it is likely that more than one DMA slave controllers in
 * the world will support the configuration option, then make it generic.
 * If not: if it is fixed so that it be sent in static from the platform
 * data, then prefer to do that.
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 */
struct dma_slave_config {
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	enum dma_transfer_direction direction;
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	phys_addr_t src_addr;
	phys_addr_t dst_addr;
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	enum dma_slave_buswidth src_addr_width;
	enum dma_slave_buswidth dst_addr_width;
	u32 src_maxburst;
	u32 dst_maxburst;
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	u32 src_port_window_size;
	u32 dst_port_window_size;
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	bool device_fc;
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	unsigned int slave_id;
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};

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/**
 * enum dma_residue_granularity - Granularity of the reported transfer residue
 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
 *  DMA channel is only able to tell whether a descriptor has been completed or
 *  not, which means residue reporting is not supported by this channel. The
 *  residue field of the dma_tx_state field will always be 0.
 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
 *  completed segment of the transfer (For cyclic transfers this is after each
 *  period). This is typically implemented by having the hardware generate an
 *  interrupt after each transferred segment and then the drivers updates the
 *  outstanding residue by the size of the segment. Another possibility is if
 *  the hardware supports scatter-gather and the segment descriptor has a field
 *  which gets set after the segment has been completed. The driver then counts
 *  the number of segments without the flag set to compute the residue.
 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
 *  burst. This is typically only supported if the hardware has a progress
 *  register of some sort (E.g. a register with the current read/write address
 *  or a register with the amount of bursts/beats/bytes that have been
 *  transferred or still need to be transferred).
 */
enum dma_residue_granularity {
	DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
	DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
	DMA_RESIDUE_GRANULARITY_BURST = 2,
};

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/* struct dma_slave_caps - expose capabilities of a slave channel only
 *
 * @src_addr_widths: bit mask of src addr widths the channel supports
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 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
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 * @directions: bit mask of slave direction the channel supported
 * 	since the enum dma_transfer_direction is not defined as bits for each
 * 	type of direction, the dma controller should fill (1 << <TYPE>) and same
 * 	should be checked by controller as well
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 * @max_burst: max burst capability per-transfer
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 * @cmd_pause: true, if pause and thereby resume is supported
 * @cmd_terminate: true, if terminate cmd is supported
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 * @residue_granularity: granularity of the reported transfer residue
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 * @descriptor_reuse: if a descriptor can be reused by client and
 * resubmitted multiple times
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 */
struct dma_slave_caps {
	u32 src_addr_widths;
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	u32 dst_addr_widths;
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	u32 directions;
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	u32 max_burst;
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	bool cmd_pause;
	bool cmd_terminate;
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	enum dma_residue_granularity residue_granularity;
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	bool descriptor_reuse;
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};

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static inline const char *dma_chan_name(struct dma_chan *chan)
{
	return dev_name(&chan->dev->device);
}
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void dma_chan_cleanup(struct kref *kref);

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/**
 * typedef dma_filter_fn - callback filter for dma_request_channel
 * @chan: channel to be reviewed
 * @filter_param: opaque parameter passed through dma_request_channel
 *
 * When this optional parameter is specified in a call to dma_request_channel a
 * suitable channel is passed to this routine for further dispositioning before
 * being returned.  Where 'suitable' indicates a non-busy channel that
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 * satisfies the given capability mask.  It returns 'true' to indicate that the
 * channel is suitable.
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 */
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typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
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typedef void (*dma_async_tx_callback)(void *dma_async_param);
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enum dmaengine_tx_result {
	DMA_TRANS_NOERROR = 0,		/* SUCCESS */
	DMA_TRANS_READ_FAILED,		/* Source DMA read failed */
	DMA_TRANS_WRITE_FAILED,		/* Destination DMA write failed */
	DMA_TRANS_ABORTED,		/* Op never submitted / aborted */
};

struct dmaengine_result {
	enum dmaengine_tx_result result;
	u32 residue;
};

typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
				const struct dmaengine_result *result);

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struct dmaengine_unmap_data {
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	u8 map_cnt;
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	u8 to_cnt;
	u8 from_cnt;
	u8 bidi_cnt;
	struct device *dev;
	struct kref kref;
	size_t len;
	dma_addr_t addr[0];
};

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/**
 * struct dma_async_tx_descriptor - async transaction descriptor
 * ---dma generic offload fields---
 * @cookie: tracking cookie for this transaction, set to -EBUSY if
 *	this tx is sitting on a dependency list
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 * @flags: flags to augment operation preparation, control completion, and
 * 	communicate status
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 * @phys: physical address of the descriptor
 * @chan: target channel for this operation
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 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
 * descriptor pending. To be pushed on .issue_pending() call
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 * @callback: routine to call after this operation is complete
 * @callback_param: general parameter to pass to the callback routine
 * ---async_tx api specific fields---
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 * @next: at completion submit this descriptor
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 * @parent: pointer to the next level up in the dependency chain
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 * @lock: protect the parent and next pointers
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 */
struct dma_async_tx_descriptor {
	dma_cookie_t cookie;
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	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
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	dma_addr_t phys;
	struct dma_chan *chan;
	dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
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	int (*desc_free)(struct dma_async_tx_descriptor *tx);
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	dma_async_tx_callback callback;
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	dma_async_tx_callback_result callback_result;
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	void *callback_param;
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	struct dmaengine_unmap_data *unmap;
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#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
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	struct dma_async_tx_descriptor *next;
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	struct dma_async_tx_descriptor *parent;
	spinlock_t lock;
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#endif
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};

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#ifdef CONFIG_DMA_ENGINE
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static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
				 struct dmaengine_unmap_data *unmap)
{
	kref_get(&unmap->kref);
	tx->unmap = unmap;
}

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struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
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void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
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#else
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
				 struct dmaengine_unmap_data *unmap)
{
}
static inline struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
{
	return NULL;
}
static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
{
}
#endif
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static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
{
	if (tx->unmap) {
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		dmaengine_unmap_put(tx->unmap);
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		tx->unmap = NULL;
	}
}

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#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
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static inline void txd_lock(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
{
	BUG();
}
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
{
}
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
{
	return NULL;
}
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
{
	return NULL;
}

#else
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
{
	spin_lock_bh(&txd->lock);
}
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
{
	spin_unlock_bh(&txd->lock);
}
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
{
	txd->next = next;
	next->parent = txd;
}
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
{
	txd->parent = NULL;
}
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
{
	txd->next = NULL;
}
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
{
	return txd->parent;
}
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
{
	return txd->next;
}
#endif

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/**
 * struct dma_tx_state - filled in to report the status of
 * a transfer.
 * @last: last completed DMA cookie
 * @used: last issued DMA cookie (i.e. the one in progress)
 * @residue: the remaining number of bytes left to transmit
 *	on the selected transfer for states DMA_IN_PROGRESS and
 *	DMA_PAUSED if this is implemented in the driver, else 0
 */
struct dma_tx_state {
	dma_cookie_t last;
	dma_cookie_t used;
	u32 residue;
};

621 622 623 624 625 626 627 628 629 630 631 632 633 634
/**
 * enum dmaengine_alignment - defines alignment of the DMA async tx
 * buffers
 */
enum dmaengine_alignment {
	DMAENGINE_ALIGN_1_BYTE = 0,
	DMAENGINE_ALIGN_2_BYTES = 1,
	DMAENGINE_ALIGN_4_BYTES = 2,
	DMAENGINE_ALIGN_8_BYTES = 3,
	DMAENGINE_ALIGN_16_BYTES = 4,
	DMAENGINE_ALIGN_32_BYTES = 5,
	DMAENGINE_ALIGN_64_BYTES = 6,
};

635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660
/**
 * struct dma_slave_map - associates slave device and it's slave channel with
 * parameter to be used by a filter function
 * @devname: name of the device
 * @slave: slave channel name
 * @param: opaque parameter to pass to struct dma_filter.fn
 */
struct dma_slave_map {
	const char *devname;
	const char *slave;
	void *param;
};

/**
 * struct dma_filter - information for slave device/channel to filter_fn/param
 * mapping
 * @fn: filter function callback
 * @mapcnt: number of slave device/channel in the map
 * @map: array of channel to filter mapping data
 */
struct dma_filter {
	dma_filter_fn fn;
	int mapcnt;
	const struct dma_slave_map *map;
};

661 662 663
/**
 * struct dma_device - info on the entity supplying DMA services
 * @chancnt: how many DMA channels are supported
664
 * @privatecnt: how many DMA channels are requested by dma_request_channel
665 666
 * @channels: the list of struct dma_chan
 * @global_node: list_head for global dma_device_list
667
 * @filter: information for device/slave to filter function/param mapping
668 669
 * @cap_mask: one or more dma_capability flags
 * @max_xor: maximum number of xor sources, 0 if no capability
670
 * @max_pq: maximum number of PQ sources and PQ-continue capability
671 672 673
 * @copy_align: alignment shift for memcpy operations
 * @xor_align: alignment shift for xor operations
 * @pq_align: alignment shift for pq operations
674
 * @fill_align: alignment shift for memset operations
675
 * @dev_id: unique device ID
676
 * @dev: struct device reference for dma mapping api
677 678 679 680 681 682
 * @src_addr_widths: bit mask of src addr widths the device supports
 * @dst_addr_widths: bit mask of dst addr widths the device supports
 * @directions: bit mask of slave direction the device supports since
 * 	the enum dma_transfer_direction is not defined as bits for
 * 	each type of direction, the dma controller should fill (1 <<
 * 	<TYPE>) and same should be checked by controller as well
683
 * @max_burst: max burst capability per-transfer
684 685
 * @residue_granularity: granularity of the transfer residue reported
 *	by tx_status
686 687 688
 * @device_alloc_chan_resources: allocate resources and return the
 *	number of allocated descriptors
 * @device_free_chan_resources: release DMA channel's resources
689 690
 * @device_prep_dma_memcpy: prepares a memcpy operation
 * @device_prep_dma_xor: prepares a xor operation
691
 * @device_prep_dma_xor_val: prepares a xor validation operation
692 693
 * @device_prep_dma_pq: prepares a pq operation
 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
694
 * @device_prep_dma_memset: prepares a memset operation
695
 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
696
 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
697
 * @device_prep_slave_sg: prepares a slave dma operation
698 699 700
 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
 *	The function takes a buffer of size buf_len. The callback function will
 *	be called after period_len bytes have been transferred.
701
 * @device_prep_interleaved_dma: Transfer expression in a generic way.
702
 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
703 704
 * @device_config: Pushes a new configuration to a channel, return 0 or an error
 *	code
705 706 707 708
 * @device_pause: Pauses any transfer happening on a channel. Returns
 *	0 or an error code
 * @device_resume: Resumes any transfer on a channel previously
 *	paused. Returns 0 or an error code
709 710
 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
 *	or an error code
711 712
 * @device_synchronize: Synchronizes the termination of a transfers to the
 *  current context.
713 714
 * @device_tx_status: poll for transaction completion, the optional
 *	txstate parameter can be supplied with a pointer to get a
715
 *	struct with auxiliary transfer status information, otherwise the call
716
 *	will just return a simple status code
717
 * @device_issue_pending: push pending transactions to hardware
718
 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
719 720 721 722
 */
struct dma_device {

	unsigned int chancnt;
723
	unsigned int privatecnt;
724 725
	struct list_head channels;
	struct list_head global_node;
726
	struct dma_filter filter;
727
	dma_cap_mask_t  cap_mask;
728 729
	unsigned short max_xor;
	unsigned short max_pq;
730 731 732 733
	enum dmaengine_alignment copy_align;
	enum dmaengine_alignment xor_align;
	enum dmaengine_alignment pq_align;
	enum dmaengine_alignment fill_align;
734
	#define DMA_HAS_PQ_CONTINUE (1 << 15)
735 736

	int dev_id;
737
	struct device *dev;
738

739 740 741
	u32 src_addr_widths;
	u32 dst_addr_widths;
	u32 directions;
742
	u32 max_burst;
743
	bool descriptor_reuse;
744 745
	enum dma_residue_granularity residue_granularity;

746
	int (*device_alloc_chan_resources)(struct dma_chan *chan);
747
	void (*device_free_chan_resources)(struct dma_chan *chan);
748 749

	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
750
		struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
751
		size_t len, unsigned long flags);
752
	struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
753
		struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
754
		unsigned int src_cnt, size_t len, unsigned long flags);
755
	struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
756
		struct dma_chan *chan, dma_addr_t *src,	unsigned int src_cnt,
757
		size_t len, enum sum_check_flags *result, unsigned long flags);
758 759 760 761 762 763 764 765
	struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
		struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
		unsigned int src_cnt, const unsigned char *scf,
		size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
		struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
		unsigned int src_cnt, const unsigned char *scf, size_t len,
		enum sum_check_flags *pqres, unsigned long flags);
766 767 768
	struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags);
769 770 771
	struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
		struct dma_chan *chan, struct scatterlist *sg,
		unsigned int nents, int value, unsigned long flags);
772
	struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
773
		struct dma_chan *chan, unsigned long flags);
774 775 776 777 778
	struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
		struct dma_chan *chan,
		struct scatterlist *dst_sg, unsigned int dst_nents,
		struct scatterlist *src_sg, unsigned int src_nents,
		unsigned long flags);
779

780 781
	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
		struct dma_chan *chan, struct scatterlist *sgl,
782
		unsigned int sg_len, enum dma_transfer_direction direction,
783
		unsigned long flags, void *context);
784 785
	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
786
		size_t period_len, enum dma_transfer_direction direction,
787
		unsigned long flags);
788 789 790
	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
		struct dma_chan *chan, struct dma_interleaved_template *xt,
		unsigned long flags);
791 792 793
	struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
		struct dma_chan *chan, dma_addr_t dst, u64 data,
		unsigned long flags);
794 795 796

	int (*device_config)(struct dma_chan *chan,
			     struct dma_slave_config *config);
797 798
	int (*device_pause)(struct dma_chan *chan);
	int (*device_resume)(struct dma_chan *chan);
799
	int (*device_terminate_all)(struct dma_chan *chan);
800
	void (*device_synchronize)(struct dma_chan *chan);
801

802 803 804
	enum dma_status (*device_tx_status)(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate);
805
	void (*device_issue_pending)(struct dma_chan *chan);
806 807
};

808 809 810
static inline int dmaengine_slave_config(struct dma_chan *chan,
					  struct dma_slave_config *config)
{
811 812 813
	if (chan->device->device_config)
		return chan->device->device_config(chan, config);

814
	return -ENOSYS;
815 816
}

817 818 819 820 821
static inline bool is_slave_direction(enum dma_transfer_direction direction)
{
	return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
}

822
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
823
	struct dma_chan *chan, dma_addr_t buf, size_t len,
824
	enum dma_transfer_direction dir, unsigned long flags)
825 826
{
	struct scatterlist sg;
827 828 829
	sg_init_table(&sg, 1);
	sg_dma_address(&sg) = buf;
	sg_dma_len(&sg) = len;
830

831 832 833
	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
		return NULL;

834 835
	return chan->device->device_prep_slave_sg(chan, &sg, 1,
						  dir, flags, NULL);
836 837
}

838 839 840 841
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
	enum dma_transfer_direction dir, unsigned long flags)
{
842 843 844
	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
		return NULL;

845
	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
846
						  dir, flags, NULL);
847 848
}

849 850 851 852 853 854 855
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
struct rio_dma_ext;
static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
	enum dma_transfer_direction dir, unsigned long flags,
	struct rio_dma_ext *rio_ext)
{
856 857 858
	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
		return NULL;

859 860 861 862 863
	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
						  dir, flags, rio_ext);
}
#endif

864 865
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
866 867
		size_t period_len, enum dma_transfer_direction dir,
		unsigned long flags)
868
{
869 870 871
	if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
		return NULL;

872
	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
873
						period_len, dir, flags);
874 875 876 877 878 879
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
		struct dma_chan *chan, struct dma_interleaved_template *xt,
		unsigned long flags)
{
880 881 882
	if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
		return NULL;

883
	return chan->device->device_prep_interleaved_dma(chan, xt, flags);
884 885
}

886 887 888 889
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags)
{
890
	if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
891 892 893 894 895 896
		return NULL;

	return chan->device->device_prep_dma_memset(chan, dest, value,
						    len, flags);
}

897 898 899 900 901 902 903 904 905 906 907
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
		size_t len, unsigned long flags)
{
	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
		return NULL;

	return chan->device->device_prep_dma_memcpy(chan, dest, src,
						    len, flags);
}

908 909 910 911 912 913
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
		struct dma_chan *chan,
		struct scatterlist *dst_sg, unsigned int dst_nents,
		struct scatterlist *src_sg, unsigned int src_nents,
		unsigned long flags)
{
914 915 916
	if (!chan || !chan->device || !chan->device->device_prep_dma_sg)
		return NULL;

917 918 919 920
	return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
			src_sg, src_nents, flags);
}

921 922 923 924 925 926 927
/**
 * dmaengine_terminate_all() - Terminate all active DMA transfers
 * @chan: The channel for which to terminate the transfers
 *
 * This function is DEPRECATED use either dmaengine_terminate_sync() or
 * dmaengine_terminate_async() instead.
 */
928 929
static inline int dmaengine_terminate_all(struct dma_chan *chan)
{
930 931 932
	if (chan->device->device_terminate_all)
		return chan->device->device_terminate_all(chan);

933
	return -ENOSYS;
934 935
}

936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984
/**
 * dmaengine_terminate_async() - Terminate all active DMA transfers
 * @chan: The channel for which to terminate the transfers
 *
 * Calling this function will terminate all active and pending descriptors
 * that have previously been submitted to the channel. It is not guaranteed
 * though that the transfer for the active descriptor has stopped when the
 * function returns. Furthermore it is possible the complete callback of a
 * submitted transfer is still running when this function returns.
 *
 * dmaengine_synchronize() needs to be called before it is safe to free
 * any memory that is accessed by previously submitted descriptors or before
 * freeing any resources accessed from within the completion callback of any
 * perviously submitted descriptors.
 *
 * This function can be called from atomic context as well as from within a
 * complete callback of a descriptor submitted on the same channel.
 *
 * If none of the two conditions above apply consider using
 * dmaengine_terminate_sync() instead.
 */
static inline int dmaengine_terminate_async(struct dma_chan *chan)
{
	if (chan->device->device_terminate_all)
		return chan->device->device_terminate_all(chan);

	return -EINVAL;
}

/**
 * dmaengine_synchronize() - Synchronize DMA channel termination
 * @chan: The channel to synchronize
 *
 * Synchronizes to the DMA channel termination to the current context. When this
 * function returns it is guaranteed that all transfers for previously issued
 * descriptors have stopped and and it is safe to free the memory assoicated
 * with them. Furthermore it is guaranteed that all complete callback functions
 * for a previously submitted descriptor have finished running and it is safe to
 * free resources accessed from within the complete callbacks.
 *
 * The behavior of this function is undefined if dma_async_issue_pending() has
 * been called between dmaengine_terminate_async() and this function.
 *
 * This function must only be called from non-atomic context and must not be
 * called from within a complete callback of a descriptor submitted on the same
 * channel.
 */
static inline void dmaengine_synchronize(struct dma_chan *chan)
{
985 986
	might_sleep();

987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017
	if (chan->device->device_synchronize)
		chan->device->device_synchronize(chan);
}

/**
 * dmaengine_terminate_sync() - Terminate all active DMA transfers
 * @chan: The channel for which to terminate the transfers
 *
 * Calling this function will terminate all active and pending transfers
 * that have previously been submitted to the channel. It is similar to
 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
 * stopped and that all complete callbacks have finished running when the
 * function returns.
 *
 * This function must only be called from non-atomic context and must not be
 * called from within a complete callback of a descriptor submitted on the same
 * channel.
 */
static inline int dmaengine_terminate_sync(struct dma_chan *chan)
{
	int ret;

	ret = dmaengine_terminate_async(chan);
	if (ret)
		return ret;

	dmaengine_synchronize(chan);

	return 0;
}

1018 1019
static inline int dmaengine_pause(struct dma_chan *chan)
{
1020 1021 1022
	if (chan->device->device_pause)
		return chan->device->device_pause(chan);

1023
	return -ENOSYS;
1024 1025 1026 1027
}

static inline int dmaengine_resume(struct dma_chan *chan)
{
1028 1029 1030
	if (chan->device->device_resume)
		return chan->device->device_resume(chan);

1031
	return -ENOSYS;
1032 1033
}

1034 1035 1036 1037 1038 1039
static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
	dma_cookie_t cookie, struct dma_tx_state *state)
{
	return chan->device->device_tx_status(chan, cookie, state);
}

1040
static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1041 1042 1043 1044
{
	return desc->tx_submit(desc);
}

1045 1046
static inline bool dmaengine_check_align(enum dmaengine_alignment align,
					 size_t off1, size_t off2, size_t len)
1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
{
	size_t mask;

	if (!align)
		return true;
	mask = (1 << align) - 1;
	if (mask & (off1 | off2 | len))
		return false;
	return true;
}

static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
				       size_t off2, size_t len)
{
	return dmaengine_check_align(dev->copy_align, off1, off2, len);
}

static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
				      size_t off2, size_t len)
{
	return dmaengine_check_align(dev->xor_align, off1, off2, len);
}

static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
				     size_t off2, size_t len)
{
	return dmaengine_check_align(dev->pq_align, off1, off2, len);
}

1076 1077 1078 1079 1080 1081
static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
				       size_t off2, size_t len)
{
	return dmaengine_check_align(dev->fill_align, off1, off2, len);
}

1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
static inline void
dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
{
	dma->max_pq = maxpq;
	if (has_pq_continue)
		dma->max_pq |= DMA_HAS_PQ_CONTINUE;
}

static inline bool dmaf_continue(enum dma_ctrl_flags flags)
{
	return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
}

static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
{
	enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;

	return (flags & mask) == mask;
}

static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
{
	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
}

1107
static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
{
	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
}

/* dma_maxpq - reduce maxpq in the face of continued operations
 * @dma - dma device with PQ capability
 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
 *
 * When an engine does not support native continuation we need 3 extra
 * source slots to reuse P and Q with the following coefficients:
 * 1/ {00} * P : remove P from Q', but use it as a source for P'
 * 2/ {01} * Q : use Q to continue Q' calculation
 * 3/ {00} * Q : subtract Q from P' to cancel (2)
 *
 * In the case where P is disabled we only need 1 extra source:
 * 1/ {01} * Q : use Q to continue Q' calculation
 */
static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
{
	if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
		return dma_dev_to_maxpq(dma);
	else if (dmaf_p_disabled_continue(flags))
		return dma_dev_to_maxpq(dma) - 1;
	else if (dmaf_continue(flags))
		return dma_dev_to_maxpq(dma) - 3;
	BUG();
}

1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
				      size_t dir_icg)
{
	if (inc) {
		if (dir_icg)
			return dir_icg;
		else if (sgl)
			return icg;
	}

	return 0;
}

static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
					   struct data_chunk *chunk)
{
	return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
				 chunk->icg, chunk->dst_icg);
}

static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
					   struct data_chunk *chunk)
{
	return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
				 chunk->icg, chunk->src_icg);
}

1163 1164
/* --- public DMA engine API --- */

1165
#ifdef CONFIG_DMA_ENGINE
1166 1167
void dmaengine_get(void);
void dmaengine_put(void);
1168 1169 1170 1171 1172 1173 1174 1175 1176
#else
static inline void dmaengine_get(void)
{
}
static inline void dmaengine_put(void)
{
}
#endif

1177 1178 1179
#ifdef CONFIG_ASYNC_TX_DMA
#define async_dmaengine_get()	dmaengine_get()
#define async_dmaengine_put()	dmaengine_put()
1180
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1181 1182
#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
#else
1183
#define async_dma_find_channel(type) dma_find_channel(type)
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#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
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#else
static inline void async_dmaengine_get(void)
{
}
static inline void async_dmaengine_put(void)
{
}
static inline struct dma_chan *
async_dma_find_channel(enum dma_transaction_type type)
{
	return NULL;
}
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#endif /* CONFIG_ASYNC_TX_DMA */
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void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
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				  struct dma_chan *chan);
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static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
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{
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	tx->flags |= DMA_CTRL_ACK;
}

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static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags &= ~DMA_CTRL_ACK;
}

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static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
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{
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	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
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}

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#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
static inline void
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
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{
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	set_bit(tx_type, dstp->bits);
}
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#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
static inline void
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	clear_bit(tx_type, dstp->bits);
}

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#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
{
	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
}

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#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
static inline int
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
{
	return test_bit(tx_type, srcp->bits);
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}

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#define for_each_dma_cap_mask(cap, mask) \
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	for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
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/**
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 * dma_async_issue_pending - flush pending transactions to HW
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 * @chan: target DMA channel
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 *
 * This allows drivers to push copies to HW in batches,
 * reducing MMIO writes where possible.
 */
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static inline void dma_async_issue_pending(struct dma_chan *chan)
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{
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	chan->device->device_issue_pending(chan);
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}

/**
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 * dma_async_is_tx_complete - poll for transaction completion
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 * @chan: DMA channel
 * @cookie: transaction identifier to check status of
 * @last: returns last completed cookie, can be NULL
 * @used: returns last issued cookie, can be NULL
 *
 * If @last and @used are passed in, upon return they reflect the driver
 * internal state and can be used with dma_async_is_complete() to check
 * the status of multiple cookies without re-checking hardware state.
 */
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static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
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	dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
{
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	struct dma_tx_state state;
	enum dma_status status;

	status = chan->device->device_tx_status(chan, cookie, &state);
	if (last)
		*last = state.last;
	if (used)
		*used = state.used;
	return status;
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}

/**
 * dma_async_is_complete - test a cookie against chan state
 * @cookie: transaction identifier to test status of
 * @last_complete: last know completed transaction
 * @last_used: last cookie value handed out
 *
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 * dma_async_is_complete() is used in dma_async_is_tx_complete()
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 * the test logic is separated for lightweight testing of multiple cookies
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 */
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
			dma_cookie_t last_complete, dma_cookie_t last_used)
{
	if (last_complete <= last_used) {
		if ((cookie <= last_complete) || (cookie > last_used))
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			return DMA_COMPLETE;
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	} else {
		if ((cookie <= last_complete) && (cookie > last_used))
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			return DMA_COMPLETE;
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	}
	return DMA_IN_PROGRESS;
}

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static inline void
dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
{
	if (st) {
		st->last = last;
		st->used = used;
		st->residue = residue;
	}
}

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#ifdef CONFIG_DMA_ENGINE
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struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
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enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
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void dma_issue_pending_all(void);
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struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
					dma_filter_fn fn, void *fn_param);
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struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
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struct dma_chan *dma_request_chan(struct device *dev, const char *name);
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);

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void dma_release_channel(struct dma_chan *chan);
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int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
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#else
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static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
{
	return NULL;
}
static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
{
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	return DMA_COMPLETE;
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}
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static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
{
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	return DMA_COMPLETE;
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}
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static inline void dma_issue_pending_all(void)
{
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}
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static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
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					      dma_filter_fn fn, void *fn_param)
{
	return NULL;
}
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static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
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							 const char *name)
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{
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	return NULL;
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}
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static inline struct dma_chan *dma_request_chan(struct device *dev,
						const char *name)
{
	return ERR_PTR(-ENODEV);
}
static inline struct dma_chan *dma_request_chan_by_mask(
						const dma_cap_mask_t *mask)
{
	return ERR_PTR(-ENODEV);
}
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static inline void dma_release_channel(struct dma_chan *chan)
{
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}
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static inline int dma_get_slave_caps(struct dma_chan *chan,
				     struct dma_slave_caps *caps)
{
	return -ENXIO;
}
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#endif
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#define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)

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static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
{
	struct dma_slave_caps caps;

	dma_get_slave_caps(tx->chan, &caps);

	if (caps.descriptor_reuse) {
		tx->flags |= DMA_CTRL_REUSE;
		return 0;
	} else {
		return -EPERM;
	}
}

static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
{
	tx->flags &= ~DMA_CTRL_REUSE;
}

static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
{
	return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
}

static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
{
	/* this is supported for reusable desc, so check that */
	if (dmaengine_desc_test_reuse(desc))
		return desc->desc_free(desc);
	else
		return -EPERM;
}

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/* --- DMA device --- */

int dma_async_device_register(struct dma_device *device);
void dma_async_device_unregister(struct dma_device *device);
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void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
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struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
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struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
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#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
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#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
	__dma_request_slave_channel_compat(&(mask), x, y, dev, name)

static inline struct dma_chan
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*__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
				  dma_filter_fn fn, void *fn_param,
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				  struct device *dev, const char *name)
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{
	struct dma_chan *chan;

	chan = dma_request_slave_channel(dev, name);
	if (chan)
		return chan;

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	if (!fn || !fn_param)
		return NULL;

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	return __dma_request_channel(mask, fn, fn_param);
}
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#endif /* DMAENGINE_H */