Commit 2ff40400 authored by Andrew Bresticker's avatar Andrew Bresticker Committed by Ralf Baechle

of: Add binding document for MIPS GIC

The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
interrupt vectors.  It also supports a timer and software-generated
interrupts.
Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8420/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ebf71ec7
MIPS Global Interrupt Controller (GIC)
The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
It also supports local (per-processor) interrupts and software-generated
interrupts which can be used as IPIs. The GIC also includes a free-running
global timer, per-CPU count/compare timers, and a watchdog.
Required properties:
- compatible : Should be "mti,gic".
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt specifier. Should be 3.
- The first cell is the type of interrupt, local or shared.
See <include/dt-bindings/interrupt-controller/mips-gic.h>.
- The second cell is the GIC interrupt number.
- The third cell encodes the interrupt flags.
See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
flags.
Optional properties:
- reg : Base address and length of the GIC registers. If not present,
the base address reported by the hardware GCR_GIC_BASE will be used.
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
to which the GIC may not route interrupts. Valid values are 2 - 7.
This property is ignored if the CPU is started in EIC mode.
Required properties for timer sub-node:
- compatible : Should be "mti,gic-timer".
- interrupts : Interrupt for the GIC local timer.
- clock-frequency : Clock frequency at which the GIC timers operate.
Example:
gic: interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clock-frequency = <50000000>;
};
};
uart@18101400 {
...
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
...
};
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
#include <dt-bindings/interrupt-controller/irq.h>
#define GIC_SHARED 0
#define GIC_LOCAL 1
#endif
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