Commit 38705613 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'powerpc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc updates from Michael Ellerman:
 "Highlights include:

   - Support for direct mapped LPC on POWER9, giving Linux direct access
     to devices that may be on there such as a UART.

   - Memory hotplug support for the Power9 Radix MMU.

   - Add new AUX vectors describing the processor's cache geometry, to
     be used by glibc.

   - The ability for a guest to ask the hypervisor to resize the guest's
     hash table, and in addition support for doing so automatically when
     memory is hotplugged into/out-of the guest. This allows the hash
     table to be sized based on the current memory usage of the guest,
     rather than the maximum possible memory usage.

   - Implementation of optprobes (kprobe optimisation) for powerpc.

  In addition there's the topic branch shared with the KVM tree, which
  includes support for guests to use the Radix MMU on Power9.

  Thanks to:
    Alistair Popple, Andrew Donnellan, Aneesh Kumar K.V, Anju T, Anton
    Blanchard, Benjamin Herrenschmidt, Chris Packham, Daniel Axtens,
    Daniel Borkmann, David Gibson, Finn Thain, Gautham R. Shenoy, Gavin
    Shan, Greg Kurz, Joel Stanley, John Allen, Madhavan Srinivasan,
    Mahesh Salgaonkar, Markus Elfring, Michael Neuling, Nathan Fontenot,
    Naveen N. Rao, Nicholas Piggin, Paul Mackerras, Ravi Bangoria, Reza
    Arbab, Shailendra Singh, Vaibhav Jain, Wei Yongjun"

* tag 'powerpc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (129 commits)
  powerpc/mm/radix: Skip ptesync in pte update helpers
  powerpc/mm/radix: Use ptep_get_and_clear_full when clearing pte for full mm
  powerpc/mm/radix: Update pte update sequence for pte clear case
  powerpc/mm: Update PROTFAULT handling in the page fault path
  powerpc/xmon: Fix data-breakpoint
  powerpc/mm: Fix build break with BOOK3S_64=n and MEMORY_HOTPLUG=y
  powerpc/mm: Fix build break when CMA=n && SPAPR_TCE_IOMMU=y
  powerpc/mm: Fix build break with RADIX=y & HUGETLBFS=n
  powerpc/pseries: Fix typo in parameter description
  powerpc/kprobes: Remove kprobe_exceptions_notify()
  kprobes: Introduce weak variant of kprobe_exceptions_notify()
  powerpc/ftrace: Fix confusing help text for DISABLE_MPROFILE_KERNEL
  powerpc/powernv: Fix opal_exit tracepoint opcode
  powerpc: Add a prototype for mcount() so it can be versioned
  powerpc: Drop GPL from of_node_to_nid() export to match other arches
  powerpc/kprobes: Optimize kprobe in kretprobe_trampoline()
  powerpc/kprobes: Implement Optprobes
  powerpc/kprobes: Fixes for kprobe_lookup_name() on BE
  powerpc: Add helper to check if offset is within relative branch range
  powerpc/bpf: Introduce __PPC_SH64()
  ...
parents ff47d8c0 438e69b5
......@@ -5,8 +5,46 @@ The cache bindings explained below are ePAPR compliant
Required Properties:
- compatible : Should include "fsl,chip-l2-cache-controller" and "cache"
where chip is the processor (bsc9132, npc8572 etc.)
- compatible : Should include one of the following:
"fsl,8540-l2-cache-controller"
"fsl,8541-l2-cache-controller"
"fsl,8544-l2-cache-controller"
"fsl,8548-l2-cache-controller"
"fsl,8555-l2-cache-controller"
"fsl,8568-l2-cache-controller"
"fsl,b4420-l2-cache-controller"
"fsl,b4860-l2-cache-controller"
"fsl,bsc9131-l2-cache-controller"
"fsl,bsc9132-l2-cache-controller"
"fsl,c293-l2-cache-controller"
"fsl,mpc8536-l2-cache-controller"
"fsl,mpc8540-l2-cache-controller"
"fsl,mpc8541-l2-cache-controller"
"fsl,mpc8544-l2-cache-controller"
"fsl,mpc8548-l2-cache-controller"
"fsl,mpc8555-l2-cache-controller"
"fsl,mpc8560-l2-cache-controller"
"fsl,mpc8568-l2-cache-controller"
"fsl,mpc8569-l2-cache-controller"
"fsl,mpc8572-l2-cache-controller"
"fsl,p1010-l2-cache-controller"
"fsl,p1011-l2-cache-controller"
"fsl,p1012-l2-cache-controller"
"fsl,p1013-l2-cache-controller"
"fsl,p1014-l2-cache-controller"
"fsl,p1015-l2-cache-controller"
"fsl,p1016-l2-cache-controller"
"fsl,p1020-l2-cache-controller"
"fsl,p1021-l2-cache-controller"
"fsl,p1022-l2-cache-controller"
"fsl,p1023-l2-cache-controller"
"fsl,p1024-l2-cache-controller"
"fsl,p1025-l2-cache-controller"
"fsl,p2010-l2-cache-controller"
"fsl,p2020-l2-cache-controller"
"fsl,t2080-l2-cache-controller"
"fsl,t4240-l2-cache-controller"
and "cache".
- reg : Address and size of L2 cache controller registers
- cache-size : Size of the entire L2 cache
- interrupts : Error interrupt of L2 controller
......
IBM Power-Management Bindings
=============================
Linux running on baremetal POWER machines has access to the processor
idle states. The description of these idle states is exposed via the
node @power-mgt in the device-tree by the firmware.
Definitions:
----------------
Typically each idle state has the following associated properties:
- name: The name of the idle state as defined by the firmware.
- flags: indicating some aspects of this idle states such as the
extent of state-loss, whether timebase is stopped on this
idle states and so on. The flag bits are as follows:
- exit-latency: The latency involved in transitioning the state of the
CPU from idle to running.
- target-residency: The minimum time that the CPU needs to reside in
this idle state in order to accrue power-savings
benefit.
Properties
----------------
The following properties provide details about the idle states. These
properties are exposed as arrays. Each entry in the property array
provides the value of that property for the idle state associated with
the array index of that entry.
If idle-states are defined, then the properties
"ibm,cpu-idle-state-names" and "ibm,cpu-idle-state-flags" are
required. The other properties are required unless mentioned
otherwise. The length of all the property arrays must be the same.
- ibm,cpu-idle-state-names:
Array of strings containing the names of the idle states.
- ibm,cpu-idle-state-flags:
Array of unsigned 32-bit values containing the values of the
flags associated with the the aforementioned idle-states. The
flag bits are as follows:
0x00000001 /* Decrementer would stop */
0x00000002 /* Needs timebase restore */
0x00001000 /* Restore GPRs like nap */
0x00002000 /* Restore hypervisor resource from PACA pointer */
0x00004000 /* Program PORE to restore PACA pointer */
0x00010000 /* This is a nap state (POWER7,POWER8) */
0x00020000 /* This is a fast-sleep state (POWER8)*/
0x00040000 /* This is a winkle state (POWER8) */
0x00080000 /* This is a fast-sleep state which requires a */
/* software workaround for restoring the */
/* timebase (POWER8) */
0x00800000 /* This state uses SPR PMICR instruction */
/* (POWER8)*/
0x00100000 /* This is a fast stop state (POWER9) */
0x00200000 /* This is a deep-stop state (POWER9) */
- ibm,cpu-idle-state-latencies-ns:
Array of unsigned 32-bit values containing the values of the
exit-latencies (in ns) for the idle states in
ibm,cpu-idle-state-names.
- ibm,cpu-idle-state-residency-ns:
Array of unsigned 32-bit values containing the values of the
target-residency (in ns) for the idle states in
ibm,cpu-idle-state-names. On POWER8 this is an optional
property. If the property is absent, the target residency for
the "Nap", "FastSleep" are defined to 10000 and 300000000
respectively by the kernel. On POWER9 this property is required.
- ibm,cpu-idle-state-psscr:
Array of unsigned 64-bit values containing the values for the
PSSCR for each of the idle states in ibm,cpu-idle-state-names.
This property is required on POWER9 and absent on POWER8.
- ibm,cpu-idle-state-psscr-mask:
Array of unsigned 64-bit values containing the masks
indicating which psscr fields are set in the corresponding
entries of ibm,cpu-idle-state-psscr. This property is
required on POWER9 and absent on POWER8.
Whenever the firmware sets an entry in
ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that
only the Requested Level (RL) field of the corresponding entry
in ibm,cpu-idle-state-psscr should be considered by the
kernel. For such idle states, the kernel would set the
remaining fields of the psscr to the following sane-default
values.
- ESL and EC bits are to 1. So wakeup from any stop
state will be at vector 0x100.
- MTL and PSLL are set to the maximum allowed value as
per the ISA, i.e. 15.
- The Transition Rate, TR is set to the Maximum value
3.
For all the other values of the entry in
ibm,cpu-idle-state-psscr-mask, the kernel expects all the
psscr fields of the corresponding entry in
ibm,cpu-idle-state-psscr to be correctly set by the firmware.
- ibm,cpu-idle-state-pmicr:
Array of unsigned 64-bit values containing the pmicr values
for the idle states in ibm,cpu-idle-state-names. This 64-bit
register value is to be set in pmicr for the corresponding
state if the flag indicates that pmicr SPR should be set. This
is an optional property on POWER8 and is absent on
POWER9.
- ibm,cpu-idle-state-pmicr-mask:
Array of unsigned 64-bit values containing the mask indicating
which of the fields of the PMICR are set in the corresponding
entries in ibm,cpu-idle-state-pmicr. This is an optional
property on POWER8 and is absent on POWER9.
......@@ -3201,6 +3201,71 @@ struct kvm_reinject_control {
pit_reinject = 0 (!reinject mode) is recommended, unless running an old
operating system that uses the PIT for timing (e.g. Linux 2.4.x).
4.99 KVM_PPC_CONFIGURE_V3_MMU
Capability: KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3
Architectures: ppc
Type: vm ioctl
Parameters: struct kvm_ppc_mmuv3_cfg (in)
Returns: 0 on success,
-EFAULT if struct kvm_ppc_mmuv3_cfg cannot be read,
-EINVAL if the configuration is invalid
This ioctl controls whether the guest will use radix or HPT (hashed
page table) translation, and sets the pointer to the process table for
the guest.
struct kvm_ppc_mmuv3_cfg {
__u64 flags;
__u64 process_table;
};
There are two bits that can be set in flags; KVM_PPC_MMUV3_RADIX and
KVM_PPC_MMUV3_GTSE. KVM_PPC_MMUV3_RADIX, if set, configures the guest
to use radix tree translation, and if clear, to use HPT translation.
KVM_PPC_MMUV3_GTSE, if set and if KVM permits it, configures the guest
to be able to use the global TLB and SLB invalidation instructions;
if clear, the guest may not use these instructions.
The process_table field specifies the address and size of the guest
process table, which is in the guest's space. This field is formatted
as the second doubleword of the partition table entry, as defined in
the Power ISA V3.00, Book III section 5.7.6.1.
4.100 KVM_PPC_GET_RMMU_INFO
Capability: KVM_CAP_PPC_RADIX_MMU
Architectures: ppc
Type: vm ioctl
Parameters: struct kvm_ppc_rmmu_info (out)
Returns: 0 on success,
-EFAULT if struct kvm_ppc_rmmu_info cannot be written,
-EINVAL if no useful information can be returned
This ioctl returns a structure containing two things: (a) a list
containing supported radix tree geometries, and (b) a list that maps
page sizes to put in the "AP" (actual page size) field for the tlbie
(TLB invalidate entry) instruction.
struct kvm_ppc_rmmu_info {
struct kvm_ppc_radix_geom {
__u8 page_shift;
__u8 level_bits[4];
__u8 pad[3];
} geometries[8];
__u32 ap_encodings[8];
};
The geometries[] field gives up to 8 supported geometries for the
radix page table, in terms of the log base 2 of the smallest page
size, and the number of bits indexed at each level of the tree, from
the PTE level up to the PGD level in that order. Any unused entries
will have 0 in the page_shift field.
The ap_encodings gives the supported page sizes and their AP field
encodings, encoded with the AP value in the top 3 bits and the log
base 2 of the page size in the bottom 6 bits.
5. The kvm_run structure
------------------------
......@@ -3942,3 +4007,21 @@ In order to use SynIC, it has to be activated by setting this
capability via KVM_ENABLE_CAP ioctl on the vcpu fd. Note that this
will disable the use of APIC hardware virtualization even if supported
by the CPU, as it's incompatible with SynIC auto-EOI behavior.
8.3 KVM_CAP_PPC_RADIX_MMU
Architectures: ppc
This capability, if KVM_CHECK_EXTENSION indicates that it is
available, means that that the kernel can support guests using the
radix MMU defined in Power ISA V3.00 (as implemented in the POWER9
processor).
8.4 KVM_CAP_PPC_HASH_MMU_V3
Architectures: ppc
This capability, if KVM_CHECK_EXTENSION indicates that it is
available, means that that the kernel can support guests using the
hashed page table MMU defined in Power ISA V3.00 (as implemented in
the POWER9 processor), including in-memory segment tables.
......@@ -38,7 +38,7 @@ struct mac_model
#define MAC_ADB_NONE 0
#define MAC_ADB_II 1
#define MAC_ADB_IISI 2
#define MAC_ADB_EGRET 2
#define MAC_ADB_CUDA 3
#define MAC_ADB_PB1 4
#define MAC_ADB_PB2 5
......
......@@ -286,7 +286,7 @@ static struct mac_model mac_data_table[] = {
}, {
.ident = MAC_MODEL_IISI,
.name = "IIsi",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
......@@ -295,7 +295,7 @@ static struct mac_model mac_data_table[] = {
}, {
.ident = MAC_MODEL_IIVI,
.name = "IIvi",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -304,7 +304,7 @@ static struct mac_model mac_data_table[] = {
}, {
.ident = MAC_MODEL_IIVX,
.name = "IIvx",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -319,7 +319,7 @@ static struct mac_model mac_data_table[] = {
{
.ident = MAC_MODEL_CLII,
.name = "Classic II",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -352,7 +352,7 @@ static struct mac_model mac_data_table[] = {
{
.ident = MAC_MODEL_LC,
.name = "LC",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -361,7 +361,7 @@ static struct mac_model mac_data_table[] = {
}, {
.ident = MAC_MODEL_LCII,
.name = "LC II",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -370,7 +370,7 @@ static struct mac_model mac_data_table[] = {
}, {
.ident = MAC_MODEL_LCIII,
.name = "LC III",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -498,7 +498,7 @@ static struct mac_model mac_data_table[] = {
{
.ident = MAC_MODEL_P460,
.name = "Performa 460",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......@@ -575,7 +575,7 @@ static struct mac_model mac_data_table[] = {
}, {
.ident = MAC_MODEL_P600,
.name = "Performa 600",
.adb_type = MAC_ADB_IISI,
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
......
......@@ -141,54 +141,6 @@ static void pmu_write_pram(int offset, __u8 data)
#define pmu_write_pram NULL
#endif
#if 0 /* def CONFIG_ADB_MACIISI */
extern int maciisi_request(struct adb_request *req,
void (*done)(struct adb_request *), int nbytes, ...);
static long maciisi_read_time(void)
{
struct adb_request req;
long time;
if (maciisi_request(&req, NULL, 2, CUDA_PACKET, CUDA_GET_TIME))
return 0;
time = (req.reply[3] << 24) | (req.reply[4] << 16)
| (req.reply[5] << 8) | req.reply[6];
return time - RTC_OFFSET;
}
static void maciisi_write_time(long data)
{
struct adb_request req;
data += RTC_OFFSET;
maciisi_request(&req, NULL, 6, CUDA_PACKET, CUDA_SET_TIME,
(data >> 24) & 0xFF, (data >> 16) & 0xFF,
(data >> 8) & 0xFF, data & 0xFF);
}
static __u8 maciisi_read_pram(int offset)
{
struct adb_request req;
if (maciisi_request(&req, NULL, 4, CUDA_PACKET, CUDA_GET_PRAM,
(offset >> 8) & 0xFF, offset & 0xFF))
return 0;
return req.reply[3];
}
static void maciisi_write_pram(int offset, __u8 data)
{
struct adb_request req;
maciisi_request(&req, NULL, 5, CUDA_PACKET, CUDA_SET_PRAM,
(offset >> 8) & 0xFF, offset & 0xFF, data);
}
#else
#define maciisi_read_time() 0
#define maciisi_write_time(n)
#define maciisi_read_pram NULL
#define maciisi_write_pram NULL
#endif
/*
* VIA PRAM/RTC access routines
*
......@@ -457,11 +409,10 @@ void mac_pram_read(int offset, __u8 *buffer, int len)
int i;
switch(macintosh_config->adb_type) {
case MAC_ADB_IISI:
func = maciisi_read_pram; break;
case MAC_ADB_PB1:
case MAC_ADB_PB2:
func = pmu_read_pram; break;
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
func = cuda_read_pram; break;
default:
......@@ -480,11 +431,10 @@ void mac_pram_write(int offset, __u8 *buffer, int len)
int i;
switch(macintosh_config->adb_type) {
case MAC_ADB_IISI:
func = maciisi_write_pram; break;
case MAC_ADB_PB1:
case MAC_ADB_PB2:
func = pmu_write_pram; break;
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
func = cuda_write_pram; break;
default:
......@@ -499,17 +449,13 @@ void mac_pram_write(int offset, __u8 *buffer, int len)
void mac_poweroff(void)
{
/*
* MAC_ADB_IISI may need to be moved up here if it doesn't actually
* work using the ADB packet method. --David Kilzer
*/
if (oss_present) {
oss_shutdown();
} else if (macintosh_config->adb_type == MAC_ADB_II) {
via_shutdown();
#ifdef CONFIG_ADB_CUDA
} else if (macintosh_config->adb_type == MAC_ADB_CUDA) {
} else if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_shutdown();
#endif
#ifdef CONFIG_ADB_PMU68K
......@@ -549,7 +495,8 @@ void mac_reset(void)
local_irq_restore(flags);
}
#ifdef CONFIG_ADB_CUDA
} else if (macintosh_config->adb_type == MAC_ADB_CUDA) {
} else if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_restart();
#endif
#ifdef CONFIG_ADB_PMU68K
......@@ -698,13 +645,11 @@ int mac_hwclk(int op, struct rtc_time *t)
case MAC_ADB_IOP:
now = via_read_time();
break;
case MAC_ADB_IISI:
now = maciisi_read_time();
break;
case MAC_ADB_PB1:
case MAC_ADB_PB2:
now = pmu_read_time();
break;
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
now = cuda_read_time();
break;
......@@ -736,6 +681,7 @@ int mac_hwclk(int op, struct rtc_time *t)
case MAC_ADB_IOP:
via_write_time(now);
break;
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
cuda_write_time(now);
break;
......@@ -743,8 +689,6 @@ int mac_hwclk(int op, struct rtc_time *t)
case MAC_ADB_PB2:
pmu_write_time(now);
break;
case MAC_ADB_IISI:
maciisi_write_time(now);
}
}
return 0;
......
......@@ -93,12 +93,14 @@ config PPC
select HAVE_DYNAMIC_FTRACE_WITH_REGS if MPROFILE_KERNEL
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_GCC_PLUGINS
select SYSCTL_EXCEPTION_TRACE
select VIRT_TO_BUS if !PPC64
select HAVE_IDE
select HAVE_IOREMAP_PROT
select HAVE_EFFICIENT_UNALIGNED_ACCESS if !(CPU_LITTLE_ENDIAN && POWER7_CPU)
select HAVE_KPROBES
select HAVE_OPTPROBES if PPC64
select HAVE_ARCH_KGDB
select HAVE_KRETPROBES
select HAVE_ARCH_TRACEHOOK
......@@ -164,9 +166,10 @@ config PPC
select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE
select HAVE_ARCH_HARDENED_USERCOPY
select HAVE_KERNEL_GZIP
select HAVE_CONTEXT_TRACKING if PPC64
config GENERIC_CSUM
def_bool CPU_LITTLE_ENDIAN
def_bool n
config EARLY_PRINTK
bool
......@@ -390,8 +393,8 @@ config DISABLE_MPROFILE_KERNEL
be disabled also.
If you have a toolchain which supports mprofile-kernel, then you can
enable this. Otherwise leave it disabled. If you're not sure, say
"N".
disable this. Otherwise leave it enabled. If you're not sure, say
"Y".
config MPROFILE_KERNEL
depends on PPC64 && CPU_LITTLE_ENDIAN
......
......@@ -356,8 +356,7 @@ config FAIL_IOMMU
config PPC_PTDUMP
bool "Export kernel pagetable layout to userspace via debugfs"
depends on DEBUG_KERNEL
select DEBUG_FS
depends on DEBUG_KERNEL && DEBUG_FS
help
This option exports the state of the kernel pagetables to a
debugfs file. This is only useful for kernel developers who are
......
addnote
decompress_inflate.c
empty.c
hack-coff
inffast.c
......@@ -13,11 +14,13 @@ infutil.h
kernel-vmlinux.strip.c
kernel-vmlinux.strip.gz
mktree
otheros.bld
uImage
cuImage.*
dtbImage.*
*.dtb
treeImage.*
vmlinux.strip
zImage
zImage.initrd
zImage.bin.*
......@@ -26,6 +29,7 @@ zImage.coff
zImage.epapr
zImage.holly
zImage.*lds
zImage.maple
zImage.miboot
zImage.pmac
zImage.pseries
......
......@@ -26,9 +26,11 @@ CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_PERF=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BPF_SYSCALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
......@@ -79,6 +81,11 @@ CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_BPF=m
CONFIG_BPF_JIT=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
......@@ -213,10 +220,11 @@ CONFIG_HID_SUNPLUS=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_MON=m
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_POWERNV=m
......@@ -289,6 +297,7 @@ CONFIG_LOCKUP_DETECTOR=y
CONFIG_LATENCYTOP=y
CONFIG_SCHED_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_UPROBE_EVENT=y
CONFIG_CODE_PATCHING_SELFTEST=y
CONFIG_FTR_FIXUP_SELFTEST=y
CONFIG_MSI_BITMAP_SELFTEST=y
......
......@@ -14,7 +14,9 @@ CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
CONFIG_CGROUPS=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_BPF=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BPF_SYSCALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
......@@ -76,6 +78,10 @@ CONFIG_INET_IPCOMP=m
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_BRIDGE=m
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_BPF=m
CONFIG_BPF_JIT=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
......@@ -324,6 +330,7 @@ CONFIG_DEBUG_MUTEXES=y
CONFIG_LATENCYTOP=y
CONFIG_SCHED_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_UPROBE_EVENT=y
CONFIG_CODE_PATCHING_SELFTEST=y
CONFIG_FTR_FIXUP_SELFTEST=y
CONFIG_MSI_BITMAP_SELFTEST=y
......
......@@ -24,12 +24,14 @@ CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_BPF=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_SCHED=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BPF_SYSCALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
......@@ -82,6 +84,11 @@ CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_BPF=m
CONFIG_BPF_JIT=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
......@@ -289,6 +296,7 @@ CONFIG_LOCKUP_DETECTOR=y
CONFIG_LATENCYTOP=y
CONFIG_SCHED_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_UPROBE_EVENT=y
CONFIG_CODE_PATCHING_SELFTEST=y
CONFIG_FTR_FIXUP_SELFTEST=y
CONFIG_MSI_BITMAP_SELFTEST=y
......
......@@ -120,4 +120,6 @@ extern s64 __ashrdi3(s64, int);
extern int __cmpdi2(s64, s64);
extern int __ucmpdi2(u64, u64);
void _mcount(void);
#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */
......@@ -33,9 +33,9 @@
H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
#define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_PPC_64K_PAGES)
/*
* only with hash we need to use the second half of pmd page table
* only with hash 64k we need to use the second half of pmd page table
* to store pointer to deposited pgtable_t
*/
#define H_PMD_CACHE_INDEX (H_PMD_INDEX_SIZE + 1)
......
......@@ -157,6 +157,7 @@ struct mmu_hash_ops {
unsigned long addr,
unsigned char *hpte_slot_array,
int psize, int ssize, int local);