Commit e3e07b0e authored by Guido Günther's avatar Guido Günther

Merge branch 'f/4.18/drm' into imx8-4.18-wip

parents c2d26ced 976c3756
......@@ -109,6 +109,13 @@
#define RX_DT(x) REG_GET((x), 21, 16)
#define RX_VC(x) REG_GET((x), 23, 22)
/*
* DSI Video mode
*/
#define VIDEO_MODE_BURST_MODE_WITH_SYNC_PULSES 0
#define VIDEO_MODE_NON_BURST_MODE_WITH_SYNC_EVENTS BIT(0)
#define VIDEO_MODE_BURST_MODE BIT(1)
/* DSI IRQ handling */
#define IRQ_STATUS 0x2a0
#define SM_NOT_IDLE BIT(0)
......@@ -375,10 +382,13 @@ static void nwl_dsi_config_dpi(struct nwl_mipi_dsi *dsi)
!(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
if (burst_mode) {
nwl_dsi_write(dsi, VIDEO_MODE, 0x2);
nwl_dsi_write(dsi, VIDEO_MODE, VIDEO_MODE_BURST_MODE);
nwl_dsi_write(dsi, PIXEL_FIFO_SEND_LEVEL, 256);
} else {
nwl_dsi_write(dsi, VIDEO_MODE, 0x0);
nwl_dsi_write(dsi, VIDEO_MODE,
((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
VIDEO_MODE_BURST_MODE_WITH_SYNC_PULSES :
VIDEO_MODE_NON_BURST_MODE_WITH_SYNC_EVENTS));
nwl_dsi_write(dsi, PIXEL_FIFO_SEND_LEVEL, vm->hactive);
}
......@@ -458,8 +468,11 @@ static void nwl_dsi_init_interrupts(struct nwl_mipi_dsi *dsi)
nwl_dsi_write(dsi, IRQ_MASK, 0xffffffff);
nwl_dsi_write(dsi, IRQ_MASK2, 0x7);
irq_enable = ~(u32)(TX_PKT_DONE_MASK |
RX_PKT_HDR_RCVD_MASK);
irq_enable = ~(u32)(TX_PKT_DONE_MASK
| RX_PKT_HDR_RCVD_MASK
| TX_FIFO_OVFLW_MASK
| HS_TX_TIMEOUT_MASK
);
nwl_dsi_write(dsi, IRQ_MASK, irq_enable);
}
......@@ -735,6 +748,16 @@ static void nwl_dsi_finish_transmission(struct nwl_mipi_dsi *dsi, u32 status)
if (!xfer)
return;
if (status & TX_FIFO_OVFLW) {
DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow");
return;
}
if (status & HS_TX_TIMEOUT) {
DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout");
return;
}
if (xfer->direction == DSI_PACKET_SEND && status & TX_PKT_DONE) {
xfer->status = xfer->tx_len;
end_packet = true;
......@@ -758,7 +781,6 @@ static void nwl_dsi_begin_transmission(struct nwl_mipi_dsi *dsi)
u32 val;
/* Send the payload, if any */
/* TODO: Need to check the TX FIFO overflow */
length = pkt->payload_length;
payload = pkt->payload;
......@@ -782,14 +804,14 @@ static void nwl_dsi_begin_transmission(struct nwl_mipi_dsi *dsi)
nwl_dsi_write(dsi, TX_PAYLOAD, val);
break;
}
xfer->tx_len = length;
xfer->tx_len = pkt->payload_length;
/*
* Now, send the header
* header structure is:
* header[0] = Virtual Channel + Data Type
* header[1] = Word Count LSB
* header[2] = Word Count MSB
* header[1] = Word Count LSB (LP) or first param (SP)
* header[2] = Word Count MSB (LP) or first param (SP)
*/
word_count = pkt->header[1] | (pkt->header[2] << 8);
hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM)?0:1;
......
......@@ -46,18 +46,17 @@ struct jh057n {
static const struct drm_display_mode default_mode = {
.hdisplay = 720,
.hsync_start = 720 + 40 /* front porch */,
.hsync_end = 720 + 40 + 10 /* sync_len */,
.htotal = 720 + 40 + 10 + 45 /* back porch */,
.hsync_start = 720 + 90 /* front porch */,
.hsync_end = 720 + 90 + 20 /* sync_len */,
.htotal = 720 + 90 + 20 + 20 /* back porch */,
.vdisplay = 1440,
.vsync_start = 1440 + 10 /* front porch */,
.vsync_end = 1440 + 10 + 4 /* sync_len */,
.vtotal = 1440 + 10 + 4 + 11 /* back porch */,
.vsync_start = 1440 + 20 /* front porch */,
.vsync_end = 1440 + 20 + 4 /* sync_len */,
.vtotal = 1440 + 20 + 4 + 12 /* back porch */,
.vrefresh = 60, /* confirmed from qualcom XML */
/* htotal * vtotal * vrefresh / 1000 */
/* actually 71638 but then we can't use best_match=false in mixel_phy_mipi_set_phy_speed
so let's use this for now to be on the safe side */
.clock = 72000, /* kHz */
/* actually 71638 but vendor suggets 75 Mhz */
.clock = 75000, /* kHz */
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
.width_mm = 65,
.height_mm = 130,
......@@ -151,8 +150,10 @@ static int jh057n_init_sequence(struct jh057n *ctx)
0xCC, 0xCC, 0x77, 0x77);
/* setbgp is different from our first data set*/
dcs_write_seq(ctx, ST7703_CMD_SETBGP, 0x08, 0x08);
mdelay(100);
/* setvcom is different from our first data set*/
dcs_write_seq(ctx, ST7703_CMD_SETVCOM, 0x28, 0x28);
dcs_write_seq(ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
/* undocumented */
dcs_write_seq(ctx, 0xBF, 0x02, 0x11, 0x00);
dcs_write_seq(ctx, ST7703_CMD_SETGIP1, /* 63 */
......@@ -359,11 +360,14 @@ static int jh057n_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 4;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO /* mdss-dsi-panel-type */
| MIPI_DSI_MODE_VIDEO_BURST /* mdss-dsi-traffic-mode */
/* Vendor says panel does not support burst mode,
but mdss-dsi-traffic-mode says the opposite */
/* | MIPI_DSI_MODE_VIDEO_BURST */
| MIPI_DSI_MODE_VIDEO_SYNC_PULSE
/* the st7703 supports LPM and HSM */
| MIPI_DSI_MODE_LPM
/* transition into LP between transmissions */
| MIPI_DSI_CLOCK_NON_CONTINUOUS
/* allow to shut down serial clock */
/* | MIPI_DSI_CLOCK_NON_CONTINUOUS */
;
drm_panel_init(&ctx->panel);
......
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