1. 13 Jan, 2015 1 commit
  2. 10 Dec, 2014 1 commit
  3. 04 Dec, 2014 1 commit
    • Thierry Reding's avatar
      memory: Add NVIDIA Tegra memory controller support · 89184651
      Thierry Reding authored
      The memory controller on NVIDIA Tegra exposes various knobs that can be
      used to tune the behaviour of the clients attached to it.
      Currently this driver sets up the latency allowance registers to the HW
      defaults. Eventually an API should be exported by this driver (via a
      custom API or a generic subsystem) to allow clients to register latency
      This driver also registers an IOMMU (SMMU) that's implemented by the
      memory controller. It is supported on Tegra30, Tegra114 and Tegra124
      currently. Tegra20 has a GART instead.
      The Tegra SMMU operates on memory clients and SWGROUPs. A memory client
      is a unidirectional, special-purpose DMA master. A SWGROUP represents a
      set of memory clients that form a logical functional unit corresponding
      to a single device. Typically a device has two clients: one client for
      read transactions and one client for write transactions, but there are
      also devices that have only read clients, but many of them (such as the
      display controllers).
      Because there is no 1:1 relationship between memory clients and devices
      the driver keeps a table of memory clients and the SWGROUPs that they
      belong to per SoC. Note that this is an exception and due to the fact
      that the SMMU is tightly integrated with the rest of the Tegra SoC. The
      use of these tables is discouraged in drivers for generic IOMMU devices
      such as the ARM SMMU because the same IOMMU could be used in any number
      of SoCs and keeping such tables for each SoC would not scale.
      Acked-by: default avatarJoerg Roedel <jroedel@suse.de>
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
  4. 27 Nov, 2014 2 commits
  5. 26 Nov, 2014 3 commits
  6. 24 Nov, 2014 1 commit
    • Andrew Bresticker's avatar
      of: Add binding document for MIPS GIC · 2ff40400
      Andrew Bresticker authored
      The Global Interrupt Controller (GIC) present on certain MIPS systems
      can be used to route external interrupts to individual VPEs and CPU
      interrupt vectors.  It also supports a timer and software-generated
      Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
      Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: John Crispin <blogic@openwrt.org>
      Cc: David Daney <ddaney.cavm@gmail.com>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8420/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
  7. 23 Nov, 2014 2 commits
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  17. 31 Oct, 2014 9 commits
  18. 30 Oct, 2014 5 commits