Commit f5f73bb2 authored by Angus Ainslie (Purism)'s avatar Angus Ainslie (Purism)
Browse files

imx8m_som/spl.c : use the correct mux modes for GPIO pins

parent 6f9347d8
...@@ -197,9 +197,9 @@ int board_mmc_init(bd_t *bis) ...@@ -197,9 +197,9 @@ int board_mmc_init(bd_t *bis)
#define HAPTIC_nEN IMX_GPIO_NR(5, 4) #define HAPTIC_nEN IMX_GPIO_NR(5, 4)
#define IMU_INT IMX_GPIO_NR(3, 19) #define IMU_INT IMX_GPIO_NR(3, 19)
static iomux_v3_cfg_t const pwr_en_pads[] = { static iomux_v3_cfg_t const pwr_en_pads[] = {
IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL1), IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL0),
IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL1), IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL1),
IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(PAD_CTL_FSEL1), IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(PAD_CTL_FSEL5),
}; };
/* /*
......
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