As the SDP protocol use the predefined ep num for communication, we can't
change its name hence reset its ep num while do ep autoconfig, this is
only apply for SPL.
Signed-off-by: Li Jun <jun.li@nxp.com>

We read the ROM version to determine the CPU revision before B1 chip.
The rom version is 4 bytes word, it has major version at low byte,
minor version at second byte.

On B0.1 chip, the value is 0x1020 not 0x20, if reading the word and comparing
with 0x20, the result is wrong.

Fix the issue by only reading the lowest byte for major version.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8d0812e63155cca91ecb78c630a450e7d5e5fd00)

Add "clocks" command to list clocks values for core and some peripherals
on QM/QXP.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c2c9b6487440946a52564ee20c2b1943a4085152)

Enable the mtest command and add relevant configurations for tested memory
range to all validation boards and EVK board.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit d92447e705ff6f077c602d340c01535ccee0ea66)

Enable the mtest command and add relevant configurations for tested memory
range to all ARM2 boards and EVK board.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit bb3dfa130dd0af57dfe7a41869f6ecd843e6c558)

Enable the mtest command and add relevant configurations for tested memory
range.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4bfe6f1e7527921d9f02dbd37eea8924dd6d3336)

On iMX8MQ Rev B1, reading from fuse box is not allowed. The
OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa
for chip rev. So u-boot has to disable the fuse sense function for it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit da95f60611e8859eba3e7ccb715fdce4d6376774)

The mscale B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id.
It returns a magic number 0xff0055aa.
Update get_cpu_rev to support this way, also enable OCOTP clock to allow
access OCOTP register.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 866631c2140b9352c6f74ec36d1a51fea40c0445)

Add common CHIP_REV_2_1 for chip revision 2.1
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f7fc83ffb0f204d9f6ec6c77c08d23869d9ecde4)

ipg_stop from GPC is not connected to WDOG directly, the sec_debug clock is
used to sample the ipg_stop from GPC. So when this clock is off, ipg_stop input
of WDOG can’t assert, WDOG will fail to stop in DSM mode.
Enable this clock forever in SPL, so other SW don't need to touch it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 1da6c9b3a837d15c25086af449462d5e8b56c290)

enhance memory controller performance and QoS setting
Signed-off-by: Tom.zheng <haidong.zheng@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit ae7b37d3ed72bad542c8e77db4bbc0325180d6d2)

After executing each ucmd, the ucmd callback function always call fastboot_setup
to setup some enviroments.

Because the mmc will be switched to user area by calling blk_get_dev in _fastboot_load_partitions.
When running "mmc partconf" by ucmd, the PART_CONFIG EXTCSD is updated, but the part_config and
hwpart variables in mmc and blk structure are not synced. So the old value will write to
PART_CONFIG EXTCSD again when switch to user area.

This patch changes the fastboot_setup, only load the partitions when the storage device is changed.
Also force to re-init mmc before loading the partitions to sync mmc variables.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c9cd93b25586ecd4ce9178da7b8141f60cdd9deb)

Enable RTC in bootloader to avoid rtc time less than jiffies time
when linux first bootup after RTC lose power.
It will cause the issue as
MA-9554[Android_6DL_SD]RTC: Sometimes the RTC reset to the initial
time 1970 after softare reboot the first time. 40%

Change-Id: I0c87180640be98a2c928a30c6949f91f4515844d
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>