The current FSP 2.0 headers do not match the headers from the official
FSP 2.0 image that was released on github [1].

The SpiFlashCfgLockDown, PcieRpClkSrcNumber and IslVrCmd fields in the
FspsUpd structure do not exist in the github version, but they are kept
here because they are used by coreboot and are not causing problems when
set as it only changed UnusedUpdSpace in the github UPD.

The MEMORY_INFO_DATA_HOB structure has its EfiHobGuidType field removed
because hob_header_to_extension_hob in drivers/intel/fsp2_0/
called by fsp_find_extension_hob_by_guid will actually remove it before
returning the structure pointer.

[1] https://github.com/IntelFsp/FSP/tree/Kabylake/KabylakeFspBinPkg

Change-Id: I233bf7cf6f62e9e1b389d42a09461717a3285f0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>

Code is very similar to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different

Change-Id: I86d099ba1919009ecc6cc8ec7af4dbabc68ec3cf
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>

Change-Id: I7ffcea7bff988d3d4269e1334fc938932aed2eb4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>

The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.

Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>

The Advanced Error Reporting capability was hardcoded in the PCIe
extended capability list, but it might not always be possible.

The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.

Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>

I finally found out why disabling the L1 sub state option did not
prevent some NVMe drives from locking up in L1 substate. I expect
that the disabled L1 substate initialization that coreboot does
is negated because Linux might itself configure it if it finds the
capability enabled on the PCIe root port.

Removing the capability from the PCIe root port when L1 sub states
are disabled in the configuration should fix the problem.

This was not tested because it's a difficult issue to reproduce and
I do not have the problematic hardware that caused it anymore.

Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>

Now that __aligned is around, take advantage of it.

Change-Id: I93cdbe108d752088f34d3f5722dce5d9b90bcdc3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26022Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

barrier_wait_timeout() was not used anywhere in the code. The
remaining two functions, barrier_wait() and release_barrier(), are
not used anywhere but the mp code.

Change-Id: If09991f95306becc68b6008ae6448695fb4a2dca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26021Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The existing logic to set up CsMux67 used an incorrect mask
and comparison value due to a copy + paste editing error.

Use the correct mask and comparison value for the last two
values.

Commit cf1cb5b2 did the same
for CsMux45 but missed this one.

Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25994Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.

Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.

Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

Add device tree options to enable beeps when exceeding temperature,
voltage, and fan limits. As of this commit, setting voltage and fan
limits is not implemented.

Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22141Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26013Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26012Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26011Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: If9c122efbb7dbab7d834372da3c1c70463be7a77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26010Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: Idff2ec30f0b8c9a49f4369e231be92cbc8070dc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26009Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: Ia25c5097d4cfa979c18a855e656ad794c2f0260c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26008Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: I839533a33aa54df4efed3f372c6f88e79b0b559b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26007Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: I14c0db71ffa5faa8321c88c9c75c0c18a70910e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26006Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: I5eb858df7b69a7177564c883b81177ffadc63691
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26005Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: I6f3efd8c9be7f9fb83b373fbee311b06cde54181
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26004Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26003Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of `device_t` has been abandoned in ramstage.

Change-Id: Ic25d1eb3c7f0ed5b65aa1cf9e16c39415b7cd3c7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26002Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I2e1e494f40bf2316e02a96759a92c933ee11fbab
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26024Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I35fcf25906bf7fe5af133618654bb121404743fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26025Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I4f57376138725804133059c785e89e095fd6a759
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26000Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Add method to walk memory tables from OS point of view.
The tables don't change when modifiying bootmem entries and doesn't contain
bootmem specific tags.

Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25747Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Add a method to walk bootmem memory tables and call a function
for each memory range. The tables might not match with OS sight
of view.
Return true if the callback function returned false.

Required for FIT support in coreboot to find a usable RAM region.

Tested on Cavium SoC.

Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25583Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:

BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
                  should not be touched by bootmem (by example: stack,
                  TTB, program, ...).
BM_MEM_PAYLOAD  : Memory where any kind of payload resides and that should
                  not be touched by bootmem.

Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.

Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.

ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.

ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.

Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4528eb064e8b9c5ebb235ca16e13582df9efd4cd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25990Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Using da7219 mclk-name property, oscout system clock is linked
to da7219 mclk. da7219 then handles enabling/disabling of the clk.

BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver

Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25920Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Non-dts based systems can pass mclk to da7219 driver by
this property.

BUG=b:74570989
TEST=Enabled clock in kernel driver using the property

Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25919Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

oscout system clock is present in FCH misc device.
The kernel acpi misc driver will use the resource to
register oscout system clock.

BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver

Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25918Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.

BUG=b:79109029, b:69270831

Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

When the latest AGESA timestamp values were added, the descriptions
weren't added along with them.  Because of this, the cbmem tool just
shows them as "<unknown>".

Bug=b:79153552
TEST=None

Change-Id: Iad7bcd53bc6136b74d4d933d1a290feac6a0de56
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26001Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This reverts commit edf2f59b.
(google/kahlee: Resume on AC insertion)

The requirement to wake on AC insert is just to wake enough to charge,
not to wake the entire system.

BUG=b:77602394
TEST=None

Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26014Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.

BUG=b:72859972
TEST=Boot grunt

Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig.  They're actually sorted according
to the variant name, but previously, that was impossible to tell.

- Add a comment to the top of variants in Kconfig.name
- Inset each variant name.  If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.

It now looks like this:
*** Beltino ***

->  Mccloud (Acer Chromebox CXI)

->  Monroe (LG Chromebase 22CV241 & 22CB25S)

->  Panther (ASUS Chromebox CN60)

->  Tricky (Dell Chromebox 3010)

->  Zako (HP Chromebox G1)

Butterfly (HP Pavilion Chromebook 14)

Chell (HP Chromebook 13 G1)

Cheza

*** Cyan ***

Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

- Add raydium controller
- Update elan controller with reset and enable GPIOs.
- Enable 'probed' so Linux will check which controller is being used.

BUG=b:78929054
TEST=Both elan and raydium touchscreen controllers work

Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25998Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Fix (assumed) regression with commit
   ac63b415 vendorcode/amd/agesa: Fix variable length array declaration

The code used sizeof() on the struct where array length was
previously adjusted, but only f14 case was fixed accordingly.

Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26036Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>