Commit 17d07406 authored by Youness Alaoui's avatar Youness Alaoui

purism/librem15v2: Add support for Librem 15 v2

Code is very similar to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different

Change-Id: I86d099ba1919009ecc6cc8ec7af4dbabc68ec3cf
Signed-off-by: Youness Alaoui's avatarYouness Alaoui <youness.alaoui@puri.sm>
parent 4428fa9f
if BOARD_PURISM_LIBREM15_V2
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select BOARD_ROMSIZE_KB_8192
select EC_PURISM_LIBREM
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select SOC_INTEL_BROADWELL
config DRIVERS_PS2_KEYBOARD
def_bool y
help
Default PS/2 Keyboard to enabled on this board.
config DRIVERS_UART_8250IO
def_bool n
help
This platform does not have any way to get standard
serial output so disable it by default.
config PCIEXP_L1_SUB_STATE
def_bool n
config PCIEXP_AER
def_bool n
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default purism/librem15v2
config MAINBOARD_PART_NUMBER
string
default "Librem 15 v2"
config MAINBOARD_VERSION
string
default "2.0"
config MAINBOARD_FAMILY
string
default "Librem 15"
config MAX_CPUS
int
default 8
config NO_POST
def_bool y
help
This platform does not have any way to see POST codes
so disable them by default.
config PRE_GRAPHICS_DELAY
int
default 50
config VGA_BIOS_ID
string
default "8086,162b"
endif
config BOARD_PURISM_LIBREM15_V2
bool "Librem 15 v2"
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += pei_data.c
ramstage-y += pei_data.c
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define EC_SCI_GPI 10
#define PPCM_TURBO Zero
#define PPCM_NOTURBO One
#include <ec/purism/librem/acpi/ec.asl>
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB)
{
Device (LID0)
{
Name (_HID, EisaId ("PNP0C0D"))
Method (_STA)
{
Return (0xF)
}
Method (_LID)
{
Return (\_SB.PCI0.LPCB.EC.LIDS)
}
}
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Method (_STA)
{
Return (0xF)
}
Name (_PRW, Package () { 27, 4 })
}
Device (SLPB)
{
Name (_HID, EisaId ("PNP0C0E"))
Method (_STA)
{
Return (0xF)
}
}
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <drivers/pc80/pc/ps2_controller.asl>
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs)
{
acpi_init_gnvs(gnvs);
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current);
}
Category: laptop
Vendor name: Purism
Board name: Librem 15 v2
Board URL: https://puri.sm/librem-15/
ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
Release year: 2015
chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081"
# Port 0 is HDD
# Port 1 is M.2 NGFF
register "sata_port_map" = "0x3"
# Port tuning for link stability
register "sata_port0_gen3_dtle" = "7"
register "sata_port1_gen3_dtle" = "9"
register "sata_port2_gen3_dtle" = "9"
register "sata_port3_gen3_dtle" = "7"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3 - LAN
device pci 1c.3 on end # PCIe Port #4 - WiFi
device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip ec/purism/librem
device pnp 0c09.0 on end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
end
end
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x05, /* DSDT revision: ACPI v5.0 */
"COREv4", /* OEM id */
"COREBOOT", /* OEM table id */
0x20160115 /* OEM revision */
)
{
/* Some generic macros */
#include <soc/intel/broadwell/acpi/platform.asl>
/* Global NVS and variables */
#include <soc/intel/broadwell/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/broadwell/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/broadwell/acpi/systemagent.asl>
#include <soc/intel/broadwell/acpi/pch.asl>
}
}
/* Chipset specific sleep states */
#include <soc/intel/broadwell/acpi/sleepstates.asl>
/* Mainboard specific */
#include "acpi/mainboard.asl"
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &fadt->header;
memset(fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = ACPI_FADT_REV_ACPI_3_0;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
acpi_fill_in_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, header->length);
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpio.h>
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_INPUT, /* 0 */
PCH_GPIO_INPUT, /* 1 */
PCH_GPIO_INPUT, /* 2 */
PCH_GPIO_INPUT, /* 3 */
PCH_GPIO_INPUT, /* 4 */
PCH_GPIO_INPUT, /* 5 */
PCH_GPIO_INPUT, /* 6 */
PCH_GPIO_INPUT, /* 7 */
PCH_GPIO_INPUT, /* 8 */
PCH_GPIO_INPUT, /* 9 */
PCH_GPIO_ACPI_SCI, /* 10 */
PCH_GPIO_INPUT, /* 11 */
PCH_GPIO_INPUT, /* 12 */
PCH_GPIO_INPUT, /* 13 */
PCH_GPIO_INPUT, /* 14 */
PCH_GPIO_INPUT, /* 15 */
PCH_GPIO_INPUT, /* 16 */
PCH_GPIO_INPUT, /* 17 */
PCH_GPIO_NATIVE, /* 18 */
PCH_GPIO_NATIVE, /* 19 */
PCH_GPIO_INPUT, /* 20 */
PCH_GPIO_INPUT, /* 21 */
PCH_GPIO_INPUT, /* 22 */
PCH_GPIO_INPUT, /* 23 */
PCH_GPIO_INPUT, /* 24 */
PCH_GPIO_INPUT, /* 25 */
PCH_GPIO_INPUT, /* 26 */
PCH_GPIO_INPUT, /* 27 */
PCH_GPIO_INPUT, /* 28 */
PCH_GPIO_NATIVE, /* 29 */
PCH_GPIO_NATIVE, /* 30 */
PCH_GPIO_NATIVE, /* 31 */
PCH_GPIO_INPUT, /* 32 */
PCH_GPIO_INPUT, /* 33 */
PCH_GPIO_INPUT, /* 34 */
PCH_GPIO_NATIVE, /* 35 */
PCH_GPIO_NATIVE, /* 36 */
PCH_GPIO_NATIVE, /* 37 */
PCH_GPIO_INPUT, /* 38 */
PCH_GPIO_NATIVE, /* 39 */
PCH_GPIO_NATIVE, /* 40 */
PCH_GPIO_INPUT, /* 41 */
PCH_GPIO_INPUT, /* 42 */
PCH_GPIO_INPUT, /* 43 */
PCH_GPIO_INPUT, /* 44 */
PCH_GPIO_INPUT, /* 45 */
PCH_GPIO_INPUT, /* 46 */
PCH_GPIO_INPUT, /* 47 */
PCH_GPIO_INPUT, /* 48 */
PCH_GPIO_INPUT, /* 49 */
PCH_GPIO_INPUT, /* 50 */
PCH_GPIO_INPUT, /* 51 */
PCH_GPIO_INPUT, /* 52 */
PCH_GPIO_INPUT, /* 53 */
PCH_GPIO_INPUT, /* 54 */
PCH_GPIO_INPUT, /* 55 */
PCH_GPIO_INPUT, /* 56 */
PCH_GPIO_INPUT, /* 57 */
PCH_GPIO_INPUT, /* 58 */
PCH_GPIO_INPUT, /* 59 */
PCH_GPIO_INPUT, /* 60 */
PCH_GPIO_NATIVE, /* 61 */
PCH_GPIO_NATIVE, /* 62 */
PCH_GPIO_NATIVE, /* 63 */
PCH_GPIO_INPUT, /* 64 */
PCH_GPIO_INPUT, /* 65 */
PCH_GPIO_INPUT, /* 66 */
PCH_GPIO_INPUT, /* 67 */
PCH_GPIO_INPUT, /* 68 */
PCH_GPIO_INPUT, /* 69 */
PCH_GPIO_INPUT, /* 70 */
PCH_GPIO_NATIVE, /* 71 */
PCH_GPIO_NATIVE, /* 72 */
PCH_GPIO_INPUT, /* 73 */
PCH_GPIO_NATIVE, /* 74 */
PCH_GPIO_NATIVE, /* 75 */
PCH_GPIO_NATIVE, /* 76 */
PCH_GPIO_INPUT, /* 77 */
PCH_GPIO_INPUT, /* 78 */
PCH_GPIO_INPUT, /* 79 */
PCH_GPIO_INPUT, /* 80 */
PCH_GPIO_NATIVE, /* 81 */
PCH_GPIO_NATIVE, /* 82 */
PCH_GPIO_INPUT, /* 83 */
PCH_GPIO_INPUT, /* 84 */
PCH_GPIO_INPUT, /* 85 */
PCH_GPIO_INPUT, /* 86 */
PCH_GPIO_INPUT, /* 87 */
PCH_GPIO_INPUT, /* 88 */
PCH_GPIO_INPUT, /* 89 */
PCH_GPIO_INPUT, /* 90 */
PCH_GPIO_INPUT, /* 91 */
PCH_GPIO_INPUT, /* 92 */
PCH_GPIO_INPUT, /* 93 */
PCH_GPIO_INPUT, /* 94 */
PCH_GPIO_END
};
#endif
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
0x19910269, /* Subsystem ID */
0x0000000c, /* Number of jacks (NID entries) */
0x0017ff00, /* Function Reset */
0x0017ff00, /* Double Function Reset */
0x0017ff00,
0x0017ff00,
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */
0x00172069,
0x00172102,
0x00172291,
0x00172319,
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) */
0x01271c00,
0x01271d00,
0x01271e00,
0x01271f40,
/* Pin Complex (NID 0x14) */
0x01471c10,
0x01471d01,
0x01471e17,
0x01471f90,
/* Pin Complex (NID 0x17) */
0x01771cf0,
0x01771d11,
0x01771e11,
0x01771f41,
/* Pin Complex (NID 0x18) */
0x01871c20,
0x01871d10,
0x01871ea1,
0x01871f04,
/* Pin Complex (NID 0x19) */
0x01971c30,
0x01971d01,
0x01971ea7,
0x01971f90,
/* Pin Complex (NID 0x1A) */
0x01a71cf0,
0x01a71d11,
0x01a71e11,
0x01a71f41,
/* Pin Complex (NID 0x1B) */
0x01b71cf0,
0x01b71d11,
0x01b71e11,
0x01b71f41,
/* Pin Complex (NID 0x1D) */
0x01d71c05,
0x01d71d9d,
0x01d71e56,
0x01d71f40,
/* Pin Complex (NID 0x1E) */
0x01e71cf0,
0x01e71d11,
0x01e71e11,
0x01e71f41,
/* Pin Complex (NID 0x21) */
0x02171c1f,
0x02171d10,
0x02171e21,
0x02171f04,
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
GMA_INT15_PANEL_FIT_CENTERING,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
pei_data->dq_pins_interleaved = 1;
/* One DIMM slot */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
/* P1: Right Side Port (USB2) */
pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P2: Right Side Port (USB2) */
pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P3: Left Side Port (USB2 only) */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P4: Left Side Port (USB2 only) */
pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P5: Empty */
pei_data_usb2_port(pei_data, 4, 0x0080, 0, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P6: Bluetooth */
pei_data_usb2_port(pei_data, 5, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P7: Camera */
pei_data_usb2_port(pei_data, 6, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P8: SD Card */
pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P1: Right Side Port (USB3) */
pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
/* P2: Right Side Port (USB3) */
pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
/* P3: Empty */
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
/* P4: Empty */
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <soc/gpio.h>