Commit dd476345 authored by Youness Alaoui's avatar Youness Alaoui

purism/librem15v3: Add support for Librem 15 v3

This is a copy of the librem13v2 directory with the following
changes :
- Name and version change in Kconfig files
- Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO
- Enable PCI device 1c.4
- Change USB port definitions in devicetree

Change-Id: I572ac654d0eb9c6cb91094f8d150e6a71fb42d70
Signed-off-by: Youness Alaoui's avatarYouness Alaoui <youness.alaoui@puri.sm>
parent 1610ac6d
if BOARD_PURISM_LIBREM15_V3
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SOC_INTEL_SKYLAKE
# Workaround for EC/KBC IRQ1
select SERIRQ_CONTINUOUS_MODE
config IRQ_SLOT_COUNT
int
default 18
config MAINBOARD_VENDOR
string
default "Purism"
config MAINBOARD_FAMILY
string
default "Librem 15"
config MAINBOARD_PART_NUMBER
string
default "Librem 15 v3"
config MAINBOARD_VERSION
string
default "3.0"
config MAINBOARD_DIR
string
default "purism/librem15v3"
config MAX_CPUS
int
default 8
config NO_POST
def_bool y
help
This platform does not have any way to see POST codes
so disable them by default.
config VGA_BIOS_ID
string
default "8086,1916"
config DIMM_MAX
int
default 1
config DIMM_SPD_SIZE
int
default 512
config CPU_MICROCODE_CBFS_LEN
hex
default 0x18000
config CPU_MICROCODE_CBFS_LOC
hex
default 0xFFE115A0
config CBFS_SIZE
hex
default 0x5c0000
endif
config BOARD_PURISM_LIBREM15_V3
bool "Librem 15 v3"
##
## This file is part of the coreboot project.
##
## Copyright (C) 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += pei_data.c
ramstage-y += pei_data.c
ramstage-y += ramstage.c
ramstage-y += hda_verb.c
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define EC_SCI_GPI 0x50
#include <ec/purism/librem/acpi/ec.asl>
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB)
{
Device (LID0)
{
Name (_HID, EisaId ("PNP0C0D"))
Method (_STA)
{
Return (0xF)
}
Method (_LID)
{
Return (\_SB.PCI0.LPCB.EC.LIDS)
}
}
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Method (_STA)
{
Return (0xF)
}
Name (_PRW, Package () { 27, 4 })
}
Device (SLPB)
{
Name (_HID, EisaId ("PNP0C0E"))
Method (_STA)
{
Return (0xF)
}
}
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <drivers/pc80/pc/ps2_controller.asl>
Vendor name: Purism
Board name: Librem 15 v3
Board URL: https://puri.sm/librem-15/
Category: laptop
ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
Release year: 2017
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[2]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "IshEnable" = "0"
register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "0"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
register "pirqc_routing" = "PCH_IRQ11"
register "pirqd_routing" = "PCH_IRQ11"
register "pirqe_routing" = "PCH_IRQ11"
register "pirqf_routing" = "PCH_IRQ11"
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
#+----------------+-------+-------+-------------+-------------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 34A | 35A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------------+-------------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_RING]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
}"
# Enable Root Ports 5 and 9
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[8]" = "1"
# Enable CLKREQ# for RP9
register "PcieRpClkReqSupport[8]" = "0"
# ClkReq for NVMe - Bruteforced (no other value works)
register "PcieRpClkReqNumber[8]" = "2"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
# OC0 should be for Type-C but it seems to not have been wired, according to
# the available schematics, even though it is labeled as USB_OC_TYPEC.
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
# PL2 override 25W
register "tdp_pl2_override" = "25"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1f.0 on
chip ec/purism/librem
device pnp 0c09.0 on end
end
end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end
end
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x05, // DSDT revision: ACPI v5.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
// Some generic macros
#include <soc/intel/skylake/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/skylake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/skylake/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/skylake/acpi/systemagent.asl>
#include <soc/intel/skylake/acpi/pch.asl>
}
}
// Chipset specific sleep states
#include <soc/intel/skylake/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
}
This diff is collapsed.
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation
* (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootstate.h>
#include <chip.h>
#include <console/console.h>
#include <device/azalia_device.h>
#include <soc/intel/common/hda_verb.h>
#include <soc/pci_devs.h>
#include "hda_verb.h"
static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
/* Can support up to 4 codecs */
for (i = 3; i >= 0; i--) {
if (codec_mask & (1 << i))
hda_codec_init(base, i, cim_verb_data_size,
cim_verb_data);
}
if (pc_beep_verbs_size)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
static void mb_hda_codec_init(void *unused)
{
static struct soc_intel_skylake_config *config;
u8 *base;
struct resource *res;
u32 codec_mask;
struct device *dev;
dev = SA_DEV_ROOT;
/* Check if HDA is enabled, else return */
if (dev == NULL || dev->chip_info == NULL)
return;
config = dev->chip_info;
/*
* IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port,
* 3:I2S Ports. In HDA mode where codec need to be programmed with
* verb table
*/
if (config->IoBufferOwnership == 3)
return;
/* Find base address */
dev = dev_find_slot(0, PCH_DEVFN_HDA);
if (dev == NULL)
return;
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "HDA: base = %p\n", base);
codec_mask = hda_codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
}
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL);
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
0x19910269, /* Subsystem ID */
0x0000000c, /* Number of jacks (NID entries) */
0x0017ff00, /* Function Reset */
0x0017ff00, /* Double Function Reset */
0x0017ff00,
0x0017ff00,
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */
AZALIA_SUBVENDOR(0x0, 0x19910269),
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) */
AZALIA_PIN_CFG(0x0, 0x12, 0x40000000),
/* Pin Complex (NID 0x14) */
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
/* Pin Complex (NID 0x15) */
AZALIA_PIN_CFG(0x0, 0x15, 0x04214020),
/* Pin Complex (NID 0x17) */
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
/* Pin Complex (NID 0x18) */
AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040),
/* Pin Complex (NID 0x19) */
AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130),
/* Pin Complex (NID 0x1A) */
AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
/* Pin Complex (NID 0x1B) */
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
/* Pin Complex (NID 0x1D) */
AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505),
/* Pin Complex (NID 0x1E) */
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
};
const u32 pc_beep_verbs[] = {
};
AZALIA_ARRAY_SIZES;
#endif
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Purism SPC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <rules.h>
#include <smbios.h>
#include <string.h>
#include <cbfs.h>
#define MAX_SERIAL_LENGTH 0x100
const char *smbios_mainboard_serial_number(void)
{
static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
struct cbfsf file;
if (serial_number[0] != 0)
return serial_number;
if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
struct region_device cbfs_region;
size_t serial_len;
cbfs_file_data(&cbfs_region, &file);
serial_len = region_device_sz(&cbfs_region);
if (serial_len < MAX_SERIAL_LENGTH) {
rdev_readat(&cbfs_region, serial_number, 0, serial_len);
serial_number[serial_len] = 0;
}
} else {
strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
MAX_SERIAL_LENGTH);
}
return serial_number;
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* DQ byte map */
const u8 dq_map[2][12] = {
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
{ 0, 1, 3, 2, 4, 5, 6, 7 },
{ 1, 0, 4, 5, 2, 3, 6, 7 } };
/* Rcomp resistor */
const u16 RcompResistor[3] = { 121, 81, 100 };
/* Rcomp target */
const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
memcpy(pei_data->RcompResistor, RcompResistor,
sizeof(RcompResistor));
memcpy(pei_data->RcompTarget, RcompTarget,
sizeof(RcompTarget));
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corporation
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of