Commit ff38c84d authored by Matt DeVillier's avatar Matt DeVillier Committed by Youness Alaoui

[WIP] BDW RMRR

Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Signed-off-by: default avatarMatt DeVillier <matt.devillier@gmail.com>
parent 7267021c
......@@ -37,6 +37,8 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_SA
select HAVE_INTEL_FIRMWARE
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select HAVE_SPI_CONSOLE_SUPPORT
......
......@@ -29,6 +29,7 @@
#include <cpu/x86/tsc.h>
#include <cpu/intel/turbo.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/systemagent.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
......@@ -583,12 +584,20 @@ static unsigned long acpi_fill_dmar(unsigned long current)
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
if (igfx_dev && igfx_dev->enabled && gfxvtbar
&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
const unsigned long tmp = current;
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
/* Add RMRR entry */
tmp = current;
current += acpi_create_dmar_rmrr(current, 0,
sa_get_gsm_base(), sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
}
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
......
......@@ -94,9 +94,11 @@
/* MCHBAR */
#ifndef MCHBAR32
#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x))
#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x))
#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x))
#endif
#define MCHBAR_PEI_VERSION 0x5034
#define BIOS_RESET_CPL 0x5da8
......
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