1. 04 May, 2018 3 commits
  2. 03 May, 2018 3 commits
  3. 02 May, 2018 3 commits
  4. 30 Apr, 2018 5 commits
  5. 27 Apr, 2018 1 commit
  6. 26 Apr, 2018 4 commits
  7. 25 Apr, 2018 1 commit
    • Aaron Durbin's avatar
      arch/x86: add support for cache-as-ram paging · 0f35af8f
      Aaron Durbin authored
      Processors, such as glk, need to have paging enabled while
      in cache-as-ram mode because the front end is agressive about
      fetching lines into the L1I cache. If the line is dirty and in
      the L1D then it writes it back to "memory". However, in this case
      there is no backing store so the cache-as-ram data that was written
      back transforms to all 0xff's when read back in causing corruption.
      
      In order to mitigate the failure add x86 architecture support for
      enabling paging while in cache-as-ram mode. A Kconfig variable,
      NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
      out for page tables within the cache-as-ram region. Additionally,
      the page directory pointer table is also carved out of cache-as-ram.
      Both areas are allocated from the persist-across-stages region
      of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
      the page tables.
      
      The two paging-related areas are loaded by calling
      paging_enable_for_car() with the names of cbfs files to load the
      initial paging structures from.
      
      BUG=b:72728953
      
      Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
      Signed-off-by: default avatarAaron Durbin <adurbin@chromium.org>
      Reviewed-on: https://review.coreboot.org/25717Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
      Reviewed-by: default avatarFurquan Shaikh <furquan@google.com>
      Reviewed-by: default avatarJustin TerAvest <teravest@chromium.org>
      0f35af8f
  8. 24 Apr, 2018 5 commits
  9. 20 Apr, 2018 1 commit
  10. 12 Apr, 2018 1 commit
    • Raul E Rangel's avatar
      include/memory_info.h: Change serial number field from 5 bytes to 4 · 99f54a60
      Raul E Rangel authored
      dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
      serial number. dimm_info.serial required a 4 character ascii string with
      a null terminator.
      
      This change makes the serial field so it matches the SPD spec.
      smbios.c will then translate the byte array into hex and set it on the
      smbios table.
      
      There were only two callers that set the serial number:
      * haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
        it already matches the new contract.
      * amd_late_init.c: Previously copied the last 4 characters. Requires
        decoding the serial number into a byte array.
      
      google/cyan/spd/spd.c: This could be updated to pass the serial number,
      but it uses a hard coded spd.bin.
      
      Testing this on grunt, dmidecode now shows the full serial number:
              Serial Number: 00000000
      
      BUG=b:65403853
      TEST=tested on grunt
      
      Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
      Signed-off-by: default avatarRaul E Rangel <rrangel@chromium.org>
      Reviewed-on: https://review.coreboot.org/25343Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
      Reviewed-by: default avatarAaron Durbin <adurbin@chromium.org>
      99f54a60
  11. 11 Apr, 2018 1 commit
  12. 09 Apr, 2018 2 commits
  13. 01 Apr, 2018 2 commits
  14. 23 Mar, 2018 2 commits
  15. 14 Mar, 2018 1 commit
  16. 07 Mar, 2018 1 commit
  17. 01 Mar, 2018 1 commit
  18. 26 Feb, 2018 1 commit
  19. 20 Feb, 2018 2 commits