diff --git a/pyBusPirateLite/BBIO_base.py b/pyBusPirateLite/BBIO_base.py
index 4f01a70f26fa962b173da52d7f574bc43319a241..a80142e92907f84e0584beae5b0e2d4609fbfb1a 100755
--- a/pyBusPirateLite/BBIO_base.py
+++ b/pyBusPirateLite/BBIO_base.py
@@ -241,7 +241,6 @@ depend on the device you are interfacing with)"""
def send_start_bit(self):
- self.check_mode(['i2c', 'raw'])
self.write(0x02)
self.response(1, True)
if self.response(1, True) == '\x01':
@@ -251,7 +250,6 @@ def send_start_bit(self):
def send_stop_bit(self):
- self.check_mode(['i2c', 'raw'])
self.write(0x03)
if self.response(1, True) == 'x01':
self.recurse_end()
@@ -281,7 +279,6 @@ def bulk_trans(self, byte_count=1, byte_string=None):
In modes other than I2C I think it returns whatever data it gets while
sending, but this feature is untested. PLEASE REPORT so that I can
document it."""
-# self.check_mode(not_bb)
if byte_string is None:
pass
self.write(0x10 | (byte_count - 1))
diff --git a/pyBusPirateLite/BitBang.py b/pyBusPirateLite/BitBang.py
index ca180a1ce99cfa61ea7738dc97ccc2385fbd60c5..6f551fbcf1e12ca22267c1b8ef90a3d5825bdbdb 100644
--- a/pyBusPirateLite/BitBang.py
+++ b/pyBusPirateLite/BitBang.py
@@ -21,7 +21,7 @@ You should have received a copy of the GNU General Public License
along with pyBusPirate. If not, see .
"""
-from .BBIO_base import BBIO_base, BPError, ProtocolError
+from .BBIO_base import BBIO_base, ProtocolError
class BitBang(BBIO_base):
@@ -140,7 +140,6 @@ class BitBang(BBIO_base):
self.write(0x14)
self.timeout(self.minDelay)
ret = self.response(2, True)
- print('0: %d, 1: %d' % (ret[0], ret[1]))
voltage = (ret[0] << 8) + ret[1]
voltage = (voltage * 6.6) / 1024
return voltage
@@ -159,7 +158,6 @@ class BitBang(BBIO_base):
ret = self.response(2, True)
voltage = (ret[0] << 8) + ret[1]
voltage = (voltage * 6.6) / 1024
-# return voltage
if voltage < 10:
"""sometimes the input gets out of sync. This is the best error checking
@@ -175,14 +173,12 @@ class BitBang(BBIO_base):
def stop_getting_adc_voltages(self):
"""I was encountering problems resetting out of adc mode, so I wrote this
little function"""
- #self.check_mode('adc')
self.port.flushInput()
for i in range(5):
self.write(0x00)
#r, w, e = select.select([self.port], [], [], 0.01);
- r = self.response(1, True)
- if r:
- break
+ r = self.response(1, binary=True)
+ if r: break;
self.port.flushInput()
self.enter_bb()
return 1
@@ -210,15 +206,18 @@ class BitBang(BBIO_base):
int
Number of errors
"""
+ self.port.flushInput()
if complete is True:
self.write(0x11)
else:
self.write(0x10)
- self.timeout(self.minDelay * 50)
- errors = self.response(1)
+ self.timeout(1)
+ errors = self.response(1, binary=True)
self.write(0xff)
- if self.response(1) != '\x01':
+ resp = self.response(1, binary=True)
+ if resp != b'\x01':
raise ProtocolError('Self test did not return to bitbang mode')
+ self.timeout(self.minDelay)
return ord(errors)
def enable_PWM(self, frequency, dutycycle=.5):
diff --git a/pyBusPirateLite/I2C.py b/pyBusPirateLite/I2C.py
index b056a6b441f69f614aac2291ea1cddd74309cce0..6c3fddc300c48f387c5722d944c4d2657177dff7 100644
--- a/pyBusPirateLite/I2C.py
+++ b/pyBusPirateLite/I2C.py
@@ -73,6 +73,7 @@ class I2C(BBIO_base):
return
if self.mode != 'bb':
super(I2C, self).enter()
+
self.write(0x02)
self.timeout(self.minDelay * 10)
if self.response(4) == "I2C1":
diff --git a/pyBusPirateLite/common_functions.py b/pyBusPirateLite/common_functions.py
index 28cb8ea4fa28596761f69bca93947ba4f8784bca..0c781d79fb7b332c71c7595ca44adf9e1670c42d 100644
--- a/pyBusPirateLite/common_functions.py
+++ b/pyBusPirateLite/common_functions.py
@@ -23,7 +23,7 @@ along with pyBusPirate. If not, see .
from . import I2C
-def init_i2c(bp_device, power=True, pullups=True, speed=I2C.I2CSpeed._50KHZ):
+def init_i2c(bp_device, power=True, pullups=True, speed=I2C.I2C_speed['50KHZ']):
"""initializes i2c mode with some common settings hardwired
Parameters
@@ -93,6 +93,4 @@ def sniff_i2c_devices(bp_device, power=False):
if 0 in ack_sig:
working_addr += [n]
-
- print(working_addr)
return working_addr
diff --git a/pyBusPirateLite/rawwire.py b/pyBusPirateLite/rawwire.py
index 89fa656e59af01822f1faab2f69b26e11772a398..ee5c1fcfb52fc0cd19f72a39dc470b29feca2d82 100644
--- a/pyBusPirateLite/rawwire.py
+++ b/pyBusPirateLite/rawwire.py
@@ -23,7 +23,7 @@ You should have received a copy of the GNU General Public License
along with pyBusPirate. If not, see .
"""
-from .BBIO_base import BBIO_base, BPError, ProtocolError
+from .BBIO_base import BBIO_base
class RawWireCfg:
@@ -43,7 +43,9 @@ class RawWire(BBIO_base):
"""
if self.mode == 'raw':
return
- self.reset()
+ if self.mode != 'bb':
+ super(RawWire, self).enter()
+
self.write(0x05)
self.timeout(self.minDelay * 10)
if self.response(4) == "RAW1":
@@ -57,7 +59,6 @@ class RawWire(BBIO_base):
def start_bit(self):
"""is kept in because it was in for legacy code,
I recommend you use send_start_bit"""
- self.check_mode('raw')
self.port.write(chr(0x02))
self.timeout(0.1)
return self.response(1)
@@ -65,55 +66,46 @@ class RawWire(BBIO_base):
def stop_bit(self):
"""is kept in because it was in for legacy code,
I recommend you use send_stop_bit"""
- self.check_mode('raw')
self.port.write(chr(0x03))
self.timeout(0.1)
return self.response(1)
def read_bit(self):
- self.check_mode('raw')
self.port.write(chr(0x07))
self.timeout(0.1)
return self.response(1)
def peek(self):
- self.check_mode('raw')
self.port.write(chr(0x08))
self.timeout(0.1)
return self.response(1)
def clock_tick(self):
- self.check_mode('raw')
self.port.write(chr(0x09))
self.timeout(0.1)
return self.response(1)
def clock_low(self):
- self.check_mode('raw')
self.port.write(chr(0x0a))
self.timeout(0.1)
return self.response(1)
def clock_high(self):
- self.check_mode('raw')
self.port.write(chr(0x0b))
self.timeout(0.1)
return self.response(1)
def data_low(self):
- self.check_mode('raw')
self.port.write(chr(0x0c))
self.timeout(0.1)
return self.response(1)
def data_high(self):
- self.check_mode('raw')
self.port.write(chr(0x0d))
self.timeout(0.1)
return self.response(1)
- def wire_cfg(self, pins=0):
- self.check_mode('raw')
+ def wire_cfg(self, pins = 0):
self.port.write(chr(0x80 | pins))
self.timeout(0.1)
return self.response(1)
@@ -121,8 +113,7 @@ class RawWire(BBIO_base):
# if someone who cares could write a more user-friendly wire_cfg that would be cool
# (make it similar to my configure_peripherals)
- def bulk_clock_ticks(self, ticks=1):
- self.check_mode('raw')
+ def bulk_clock_ticks(self, ticks = 1):
self.port.write(chr(0x20 | (ticks - 1)))
self.timeout(0.1)
return self.response(1)
diff --git a/tests/test_bitbang.py b/tests/test_bitbang.py
index 587875665abfbad599921bdc9951ecda330a1325..1d05bbbc4e1729eec63fe596fd46a199707002fe 100644
--- a/tests/test_bitbang.py
+++ b/tests/test_bitbang.py
@@ -28,7 +28,6 @@ def test_connect_on_init():
def test_adc():
bb = BitBang()
value = bb.adc
- print(value)
assert 0.0 <= value <= 5.0