Commit 1e22941b authored by Martin Kepplinger's avatar Martin Kepplinger
Browse files

arm64: dts: imx8mq / librem5: upstream drivers for csi2 and mipi_csi_2

parent d724145c
......@@ -412,15 +412,8 @@
status = "okay";
};
&csi2_bridge {
fsl,mipi-mode;
&csi2 {
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
&ddrc {
......@@ -1486,23 +1479,19 @@
};
};
&mipi_csi_2 {
&mipi_csi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
mipi2_sensor_ep: endpoint@1 {
reg = <1>;
remote-endpoint = <&camera2_ep>;
data-lanes = <1 2>;
};
ports {
port@0 {
reg = <0>;
csi2_mipi_ep: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi2_ep>;
mipi2_sensor_ep: endpoint {
remote-endpoint = <&camera2_ep>;
data-lanes = <1 2>;
};
};
};
};
......
......@@ -21,8 +21,8 @@
#size-cells = <2>;
aliases {
csi1 = &mipi_csi_2;
csi0 = &mipi_csi1;
csi1 = &mipi_csi2;
ethernet0 = &fec1;
gpio0 = &gpio1;
gpio1 = &gpio2;
......@@ -1186,7 +1186,6 @@
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
power-domains = <&pgc_mipi_csi1>;
reset = <&src>;
resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
......@@ -1224,15 +1223,14 @@
};
};
mipi_csi_2: mipi_csi2@30b60000 {
compatible = "fsl,mxc-mipi-csi2_yav";
mipi_csi2: csi@30b60000 {
compatible = "fsl,imx8mq-mipi-csi2";
reg = <0x30b60000 0x1000>; /* MIPI CSI2 Controller base addr */
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_ESC>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>,
<&clk IMX8MQ_CLK_CLKO2>;
clock-names = "clk_core", "clk_esc", "clk_pxl", "clk_clko2";
<&clk IMX8MQ_CLK_CSI2_PHY_REF>;
clock-names = "core", "esc", "ui";
assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>,
<&clk IMX8MQ_CLK_CSI2_ESC>;
......@@ -1241,22 +1239,41 @@
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
power-domains = <&pgc_mipi_csi2>;
csis-phy-reset = <&src 0x50 7>;
phy-gpr = <&iomuxc_gpr 0xa4>;
resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
<&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
interconnect-names = "dram";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
csi2_mipi_ep: endpoint {
remote-endpoint = <&csi2_ep>;
};
};
};
};
csi2_bridge: csi2_bridge@30b80000 {
compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
csi2: csi@30b80000 {
compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
reg = <0x30b80000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_CSI2_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>;
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
power-domains = <&pgc_mipi_csi2>;
interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
clock-names = "mclk";
status = "disabled";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
usdhc1: mmc@30b40000 {
......
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