Commit 9441a380 authored by Angus Ainslie (Purism)'s avatar Angus Ainslie (Purism) Committed by Guido Gunther

imx-drm: forward port the DCSS and supporting drivers from 4.9

parent 94710cac
......@@ -2,5 +2,5 @@
# taken to initialize them in the correct order. Link order is the only way
# to ensure this currently.
obj-$(CONFIG_TEGRA_HOST1X) += host1x/
obj-y += drm/ vga/
obj-y += drm/ vga/ imx/
obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/
......@@ -98,6 +98,83 @@ const char *drm_get_format_name(uint32_t format, struct drm_format_name_buf *buf
}
EXPORT_SYMBOL(drm_get_format_name);
/**
* drm_fb_get_bpp_depth - get the bpp/depth values for format
* @format: pixel format (DRM_FORMAT_*)
* @depth: storage for the depth value
* @bpp: storage for the bpp value
*
* This only supports RGB formats here for compat with code that doesn't use
* pixel formats directly yet.
*/
void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth,
int *bpp)
{
struct drm_format_name_buf name_buf;
switch (format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB332:
case DRM_FORMAT_BGR233:
*depth = 8;
*bpp = 8;
break;
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_XBGR1555:
case DRM_FORMAT_RGBX5551:
case DRM_FORMAT_BGRX5551:
case DRM_FORMAT_ARGB1555:
case DRM_FORMAT_ABGR1555:
case DRM_FORMAT_RGBA5551:
case DRM_FORMAT_BGRA5551:
*depth = 15;
*bpp = 16;
break;
case DRM_FORMAT_RGB565:
case DRM_FORMAT_BGR565:
*depth = 16;
*bpp = 16;
break;
case DRM_FORMAT_RGB888:
case DRM_FORMAT_BGR888:
*depth = 24;
*bpp = 24;
break;
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_RGBX8888:
case DRM_FORMAT_BGRX8888:
*depth = 24;
*bpp = 32;
break;
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_RGBX1010102:
case DRM_FORMAT_BGRX1010102:
case DRM_FORMAT_ARGB2101010:
case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_RGBA1010102:
case DRM_FORMAT_BGRA1010102:
*depth = 30;
*bpp = 32;
break;
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_RGBA8888:
case DRM_FORMAT_BGRA8888:
*depth = 32;
*bpp = 32;
break;
default:
drm_get_format_name(format, &name_buf);
DRM_DEBUG_KMS("unsupported pixel format %s\n", name_buf.str);
*depth = 0;
*bpp = 0;
break;
}
}
EXPORT_SYMBOL(drm_fb_get_bpp_depth);
/*
* Internal function to query information for a given format. See
* drm_format_info() for the public API.
......
......@@ -177,4 +177,13 @@ config DRM_PANEL_SITRONIX_ST7789V
Say Y here if you want to enable support for the Sitronix
ST7789V controller for 240x320 LCD panels
config DRM_PANEL_FRD55
tristate "FRD55 Panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y here if you want to enable support for Emcraft FRD55
FHD MIPI DSI panel.
endmenu
......@@ -18,3 +18,4 @@ obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
obj-$(CONFIG_DRM_PANEL_FRD55) += panel-frd55.o
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config IMX8_PRG
tristate
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
config IMX8_DPRC
tristate
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
source drivers/gpu/imx/dpu/Kconfig
source drivers/gpu/imx/dpu-blit/Kconfig
source drivers/gpu/imx/dcss/Kconfig
obj-$(CONFIG_IMX8_PRG) += imx8_prg.o
obj-$(CONFIG_IMX8_DPRC) += imx8_dprc.o
obj-$(CONFIG_IMX_DPU_CORE) += dpu/
obj-$(CONFIG_IMX_DPU_BLIT) += dpu-blit/
obj-$(CONFIG_IMX_DCSS_CORE) += dcss/
config IMX_DCSS_CORE
tristate "i.MX DCSS core support"
depends on SOC_IMX8MQ
depends on RESET_CONTROLLER
select IMX_IRQSTEER
help
Choose this if you have a Freescale i.MX8MQ system and want to use the
Display Controller Sub System. This option only enables DCSS base
support.
obj-$(CONFIG_IMX_DCSS_CORE) += imx-dcss-core.o
imx-dcss-core-objs := dcss-common.o dcss-blkctl.o dcss-ctxld.o \
dcss-dpr.o dcss-dtg.o dcss-ss.o dcss-hdr10.o \
dcss-scaler.o dcss-dtrc.o dcss-dec400d.o dcss-wrscl.o \
dcss-rdsrc.o
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/device.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <soc/imx8/soc.h>
#include "dcss-prv.h"
#include <video/imx-dcss.h>
#define DCSS_BLKCTL_RESET_CTRL 0x00
#define B_CLK_RESETN BIT(0)
#define APB_CLK_RESETN BIT(1)
#define P_CLK_RESETN BIT(2)
#define RTR_CLK_RESETN BIT(3)
#define HDMI_RESETN BIT(4)
#define DCSS_BLKCTL_CONTROL0 0x10
#define HDMI_MIPI_CLK_SEL BIT(0)
#define DISPMIX_REFCLK_SEL_POS 4
#define DISPMIX_REFCLK_SEL_MASK GENMASK(5, 4)
#define DISPMIX_PIXCLK_SEL BIT(8)
#define HDMI_SRC_SECURE_EN BIT(16)
#define B0_SILICON_ID 0x20
static struct dcss_debug_reg blkctl_debug_reg[] = {
DCSS_DBG_REG(DCSS_BLKCTL_RESET_CTRL),
DCSS_DBG_REG(DCSS_BLKCTL_CONTROL0),
};
struct dcss_blkctl_priv {
struct dcss_soc *dcss;
void __iomem *base_reg;
bool hdmi_output;
u32 clk_setting;
};
#ifdef CONFIG_DEBUG_FS
void dcss_blkctl_dump_regs(struct seq_file *s, void *data)
{
struct dcss_soc *dcss = data;
int j;
seq_puts(s, ">> Dumping BLKCTL:\n");
for (j = 0; j < ARRAY_SIZE(blkctl_debug_reg); j++)
seq_printf(s, "%-35s(0x%04x) -> 0x%08x\n",
blkctl_debug_reg[j].name,
blkctl_debug_reg[j].ofs,
dcss_readl(dcss->blkctl_priv->base_reg +
blkctl_debug_reg[j].ofs));
}
#endif
static void dcss_blkctl_clk_reset(struct dcss_blkctl_priv *blkctl,
u32 assert, u32 deassert)
{
if (assert)
dcss_clr(assert, blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL);
if (deassert)
dcss_set(deassert, blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL);
}
void dcss_blkctl_cfg(struct dcss_soc *dcss)
{
struct dcss_blkctl_priv *blkctl = dcss->blkctl_priv;
if (blkctl->hdmi_output)
dcss_writel((blkctl->clk_setting ^ HDMI_MIPI_CLK_SEL),
blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
else
dcss_writel((blkctl->clk_setting ^ HDMI_MIPI_CLK_SEL) |
DISPMIX_PIXCLK_SEL,
blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
/* deassert clock domains resets */
dcss_blkctl_clk_reset(blkctl, 0, 0xffffff);
}
int dcss_blkctl_init(struct dcss_soc *dcss, unsigned long blkctl_base)
{
struct device_node *node = dcss->dev->of_node;
int len;
const char *disp_dev;
struct dcss_blkctl_priv *blkctl;
blkctl = devm_kzalloc(dcss->dev, sizeof(*blkctl), GFP_KERNEL);
if (!blkctl)
return -ENOMEM;
blkctl->base_reg = devm_ioremap(dcss->dev, blkctl_base, SZ_4K);
if (!blkctl->base_reg) {
dev_err(dcss->dev, "unable to remap BLK CTRL base\n");
return -ENOMEM;
}
blkctl->dcss = dcss;
dcss->blkctl_priv = blkctl;
disp_dev = of_get_property(node, "disp-dev", &len);
if (!disp_dev || !strncmp(disp_dev, "hdmi_disp", 9))
blkctl->hdmi_output = true;
if (imx8_get_soc_revision() == B0_SILICON_ID)
blkctl->clk_setting = HDMI_MIPI_CLK_SEL;
dcss_blkctl_cfg(dcss);
return 0;
}
void dcss_blkctl_exit(struct dcss_soc *dcss)
{
/* assert clock domains resets */
dcss_blkctl_clk_reset(dcss->blkctl_priv,
B_CLK_RESETN | APB_CLK_RESETN | P_CLK_RESETN |
HDMI_RESETN | RTR_CLK_RESETN, 0);
}
/* disabled only by cold reset/reboot */
void dcss_blkctl_hdmi_secure_src_en(struct dcss_soc *dcss)
{
struct dcss_blkctl_priv *blkctl = dcss->blkctl_priv;
dcss_set(HDMI_SRC_SECURE_EN, blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
}
EXPORT_SYMBOL(dcss_blkctl_hdmi_secure_src_en);
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/*
* Copyright (C) 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/device.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <drm/drm_fourcc.h>
#include <video/imx-dcss.h>
#include "dcss-prv.h"
#define USE_CTXLD 1
/* DEC400D registers offsets */
#define DEC400D_READCONFIG_BASE 0x800
#define DEC400D_READCONFIG(i) (DEC400D_READCONFIG_BASE + ((i) << 2))
#define COMPRESSION_ENABLE_BIT 0
#define COMPRESSION_FORMAT_BIT 3
#define COMPRESSION_ALIGN_MODE_BIT 16
#define TILE_ALIGN_MODE_BIT 22
#define TILE_MODE_BIT 25
#define DEC400D_READBUFFERBASE0 0x900
#define DEC400D_READCACHEBASE0 0x980
#define DEC400D_CONTROL 0xB00
#define DISABLE_COMPRESSION_BIT 1
#define SHADOW_TRIGGER_BIT 29
struct dcss_dec400d_priv {
struct dcss_soc *dcss;
void __iomem *dec400d_reg;
uint32_t dec400d_reg_base;
uint64_t modifier[4];
uint32_t pixel_format;
uint32_t ctx_id;
bool bypass; /* bypass or decompress */
};
static void dcss_dec400d_write(struct dcss_dec400d_priv *dec400d,
uint32_t value,
uint32_t offset)
{
#if !USE_CTXLD
dcss_writel(value, dec400d->dec400d_reg + offset);
#else
dcss_ctxld_write(dec400d->dcss, dec400d->ctx_id,
value, dec400d->dec400d_reg_base + offset);
#endif
}
int dcss_dec400d_init(struct dcss_soc *dcss, unsigned long dec400d_base)
{
struct dcss_dec400d_priv *dec400d;
dec400d = devm_kzalloc(dcss->dev, sizeof(*dec400d), GFP_KERNEL);
if (!dec400d)
return -ENOMEM;
dcss->dec400d_priv = dec400d;
dec400d->dcss = dcss;
dec400d->dec400d_reg = devm_ioremap(dcss->dev, dec400d_base, SZ_4K);
if (!dec400d->dec400d_reg) {
dev_err(dcss->dev, "dec400d: unable to remap dec400d base\n");
return -ENOMEM;
}
dec400d->dec400d_reg_base = dec400d_base;
#if USE_CTXLD
dec400d->ctx_id = CTX_SB_HP;
#endif
return 0;
}
void dcss_dec400d_exit(struct dcss_soc *dcss)
{
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
if (!IS_ERR(dec400d)) {
devm_kfree(dcss->dev, dec400d);
dcss->dec400d_priv = NULL;
}
}
void dcss_dec400d_set_format_mod(struct dcss_soc *dcss,
uint32_t fourcc,
uint32_t mod_idx,
uint64_t modifier)
{
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
if (mod_idx > 3) {
WARN_ON(1);
return;
}
if (mod_idx == 0)
dec400d->pixel_format = fourcc;
dec400d->modifier[mod_idx] = modifier;
}
EXPORT_SYMBOL(dcss_dec400d_set_format_mod);
void dcss_dec400d_bypass(struct dcss_soc *dcss)
{
uint32_t control;
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
dcss_dec400d_read_config(dcss, 0, false);
control = dcss_readl(dec400d->dec400d_reg + DEC400D_CONTROL);
pr_debug("%s: dec400d control = %#x\n", __func__, control);
control |= 0x1 << DISABLE_COMPRESSION_BIT;
dcss_dec400d_write(dec400d, control, DEC400D_CONTROL);
/* Trigger shadow registers */
control |= 0x1 << SHADOW_TRIGGER_BIT;
dcss_dec400d_write(dec400d, control, DEC400D_CONTROL);
dec400d->bypass = true;
}
EXPORT_SYMBOL(dcss_dec400d_bypass);
void dcss_dec400d_shadow_trig(struct dcss_soc *dcss)
{
uint32_t control;
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
/* do nothing */
if (dec400d->bypass == true)
return;
control = dcss_readl(dec400d->dec400d_reg + DEC400D_CONTROL);
/* Trigger shadow registers */
control |= 0x1 << SHADOW_TRIGGER_BIT;
dcss_dec400d_write(dec400d, control, DEC400D_CONTROL);
}
EXPORT_SYMBOL(dcss_dec400d_shadow_trig);
void dcss_dec400d_addr_set(struct dcss_soc *dcss,
uint32_t baddr,
uint32_t caddr)
{
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
/* set frame buffer base addr */
dcss_dec400d_write(dec400d, baddr, DEC400D_READBUFFERBASE0);
/* set tile status cache addr */
dcss_dec400d_write(dec400d, caddr, DEC400D_READCACHEBASE0);
dec400d->bypass = false;
}
EXPORT_SYMBOL(dcss_dec400d_addr_set);
void dcss_dec400d_read_config(struct dcss_soc *dcss,
uint32_t read_id,
bool compress_en)
{
uint32_t read_config = 0x0;
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
/* TODO: using 'read_id' 0 by default */
if (read_id) {
WARN_ON(1);
return;
}
if (compress_en == false)
goto config;
switch (dec400d->pixel_format) {
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XRGB8888:
read_config |= 0x0 << COMPRESSION_FORMAT_BIT;
break;
default:
/* TODO: not support yet */
WARN_ON(1);
return;
}
/* ALIGN32_BYTE */
read_config |= 0x2 << COMPRESSION_ALIGN_MODE_BIT;
/* TILE1_ALIGN */
read_config |= 0x0 << TILE_ALIGN_MODE_BIT;
/* TILE8x4 */
read_config |= 0x3 << TILE_MODE_BIT;
/* Compression Enable */
read_config |= 0x1 << COMPRESSION_ENABLE_BIT;
config:
dcss_dec400d_write(dec400d, read_config, DEC400D_READCONFIG(read_id));
}
EXPORT_SYMBOL(dcss_dec400d_read_config);
void dcss_dec400d_enable(struct dcss_soc *dcss)
{
uint32_t control;
struct dcss_dec400d_priv *dec400d = dcss->dec400d_priv;
if (dec400d->bypass)
return;
control = dcss_readl(dec400d->dec400d_reg + DEC400D_CONTROL);
/* enable compression */
control &= ~(0x1 << DISABLE_COMPRESSION_BIT);
dcss_dec400d_write(dec400d, control, DEC400D_CONTROL);
/* Trigger shadow registers */
control |= 0x1 << SHADOW_TRIGGER_BIT;
dcss_dec400d_write(dec400d, control, DEC400D_CONTROL);
}
EXPORT_SYMBOL(dcss_dec400d_enable);
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#ifndef __DCSS_PRV_H__
#define __DCSS_PRV_H__
#include <linux/pm_qos.h>
#define SET 0x04
#define CLR 0x08
#define TGL 0x0C
#define dcss_writel(v, c) writel((v), (c))
#define dcss_readl(c) readl(c)
#define dcss_set(v, c) writel((v), (c) + SET)
#define dcss_clr(v, c) writel((v), (c) + CLR)
#define dcss_toggle(v, c) writel((v), (c) + TGL)
#define dcss_update(v, m, c) writel((readl(c) & ~(m)) | (v), (c))
#define DCSS_DBG_REG(reg) {.name = #reg, .ofs = reg}
struct dcss_debug_reg {
char *name;
u32 ofs;
};
enum dcss_ctxld_ctx_type {
CTX_DB,
CTX_SB_HP, /* high-priority */
CTX_SB_LP, /* low-priority */
};
struct dcss_soc;
struct dcss_devtype;
struct dcss_soc {
struct device *dev;
const struct dcss_devtype *devtype;
u32 start_addr;
struct dcss_blkctl_priv *blkctl_priv;
struct dcss_ctxld_priv *ctxld_priv;
struct dcss_dpr_priv *dpr_priv;
struct dcss_dtg_priv *dtg_priv;
struct dcss_ss_priv *ss_priv;
struct dcss_hdr10_priv *hdr10_priv;
struct dcss_scaler_priv *scaler_priv;
struct dcss_dtrc_priv *dtrc_priv;
struct dcss_dec400d_priv *dec400d_priv;
struct dcss_wrscl_priv *wrscl_priv;
struct dcss_rdsrc_priv *rdsrc_priv;
struct clk *apb_clk;
struct clk *axi_clk;
struct clk *pdiv_clk;
struct clk *pout_clk;
struct clk *rtrm_clk;
struct clk *dtrc_clk;
void (*dcss_disable_callback)(void *data);
bool bus_freq_req;
bool clks_on;
struct pm_qos_request pm_qos_req;
};
/* BLKCTL */
int dcss_blkctl_init(struct dcss_soc *dcss, unsigned long blkctl_base);
void dcss_blkctl_cfg(struct dcss_soc *dcss);
void dcss_blkctl_exit(struct dcss_soc *dcss);
/* CTXLD */
int dcss_ctxld_init(struct dcss_soc *dcss, unsigned long ctxld_base);
void dcss_ctxld_hw_cfg(struct dcss_soc *dcss);
void dcss_ctxld_exit(struct dcss_soc *dcss);
void dcss_ctxld_write(struct dcss_soc *dcss, u32 ctx_id, u32 val, u32 reg_idx);
void dcss_ctxld_update(struct dcss_soc *dcss, u32 ctx_id, u32 val, u32 mask,
u32 reg_idx);
void dcss_ctxld_dump(struct seq_file *s, void *data);
int dcss_ctxld_resume(struct dcss_soc *dcss);
int dcss_ctxld_suspend(struct dcss_soc *dcss);
void dcss_ctxld_write_irqsafe(struct dcss_soc *dcss, u32 ctx_id, u32 val,
u32 reg_ofs);
/* DPR */
int dcss_dpr_init(struct dcss_soc *dcss, unsigned long dpr_base);
void dcss_dpr_exit(struct dcss_soc *dcss);
/* DTG */
int dcss_dtg_init(struct dcss_soc *dcss, unsigned long dtg_base);
void dcss_dtg_exit(struct dcss_soc *dcss);
void dcss_dtg_vblank_irq_enable(struct dcss_soc *dcss, bool en);
void dcss_dtg_vblank_irq_clear(struct dcss_soc *dcss);
/* SUBSAM */
int dcss_ss_init(struct dcss_soc *dcss, unsigned long subsam_base);
void dcss_ss_exit(struct dcss_soc *dcss);
/* HDR10 */
int dcss_hdr10_init(struct dcss_soc *dcss, unsigned long hdr10_base);
void dcss_hdr10_exit(struct dcss_soc *dcss);
void dcss_hdr10_cfg(struct dcss_soc *dcss);
/* SCALER */
int dcss_scaler_init(struct dcss_soc *dcss, unsigned long scaler_base);
void dcss_scaler_exit(struct dcss_soc *dcss);
/* DTRC */
int dcss_dtrc_init(struct dcss_soc *dcss, unsigned long dtrc_base);
void dcss_dtrc_exit(struct dcss_soc *dcss);
void dcss_dtrc_switch_banks(struct dcss_soc *dcss);
bool dcss_dtrc_is_running(struct dcss_soc *dcss, int ch_num);
/* DEC400d */
int dcss_dec400d_init(struct dcss_soc *dcss, unsigned long dec400d_base);
void dcss_dec400d_exit(struct dcss_soc *dcss);
/* enums common to both WRSCL and RDSRC */
enum dcss_wrscl_rdsrc_psize {
PSIZE_64,
PSIZE_128,
PSIZE_256,
PSIZE_512,
PSIZE_1024,
PSIZE_2048,
PSIZE_4096,
};
enum dcss_wrscl_rdsrc_tsize {
TSIZE_64,
TSIZE_128,
TSIZE_256,
TSIZE_512,
};
enum dcss_wrscl_rdsrc_fifo_size {
FIFO_512,
FIFO_1024,
FIFO_2048,
FIFO_4096,
};
enum dcss_wrscl_rdsrc_bpp {
BPP_38, /* 38 bit unpacked components */
BPP_32_UPCONVERT,
BPP_32_10BIT_OUTPUT,
BPP_20, /* 10-bit YUV422 */
BPP_16, /* 8-bit YUV422 */
};
/* WRSCL */
int dcss_wrscl_init(struct dcss_soc *dcss, unsigned long wrscl_base);
void dcss_wrscl_exit(struct dcss_soc *dcss);
u32 dcss_wrscl_setup(struct dcss_soc *dcss, u32 pix_format, u32 pix_clk_hz,
u32 dst_xres, u32 dst_yres);
void dcss_wrscl_enable(struct dcss_soc *dcss, bool en);
/* RDSRC */
int dcss_rdsrc_init(struct dcss_soc *dcss, unsigned long rdsrc_base);
void dcss_rdsrc_exit(struct dcss_soc *dcss);
void dcss_rdsrc_setup(struct dcss_soc *dcss, u32 pix_format, u32 dst_xres,
u32 dst_yres, u32 base_addr);
void dcss_rdsrc_enable(struct dcss_soc *dcss, bool en);
/* debug: dump registers routines */
void dcss_blkctl_dump_regs(struct seq_file *s, void *data);
void dcss_dtrc_dump_regs(struct seq_file *s, void *data);
void dcss_dpr_dump_regs(struct seq_file *s, void *data);
void dcss_dtg_dump_regs(struct seq_file *s, void *data);
void dcss_ss_dump_regs(struct seq_file *s, void *data);
void dcss_scaler_dump_regs(struct seq_file *s, void *data);
void dcss_ctxld_dump_regs(struct seq_file *s, void *data);
void dcss_hdr10_dump_regs(struct seq_file *s, void *data);
void dcss_wrscl_dump_regs(struct seq_file *s, void *data);
void dcss_rdsrc_dump_regs(struct seq_file *s, void *data);