...
 
Commits (29)
variables:
DEPS: >
build-essential gcc-aarch64-linux-gnu make device-tree-compiler
bison flex bc libssl-dev
before_script:
- export DEBIAN_FRONTEND=noninteractive
- apt-get -y update
- apt-get -y install $DEPS
.tags: &tags
tags:
- librem5
build:aarch64:
<<: *tags
stage: build
variables:
CROSS_BUILD: "ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-"
script:
- cp arch/arm64/configs/librem5-devkit_defconfig .config
- make ${CROSS_BUILD} olddefconfig
- make -j 4 ${CROSS_BUILD} Image dtbs modules
- make -j 4 ${CROSS_BUILD} INSTALL_MOD_PATH=modules/ modules_install
artifacts:
paths:
- arch/arm64/boot/Image
- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dtb
- modules/
expire_in: 1 week
......@@ -23,6 +23,20 @@ Required properties:
Optional properties:
- clock-output-names : Should contain name for output clock.
- rohm,reset-snvs-powered : Transfer BD718x7 to SNVS state at reset.
The BD718x7 supports two different HW states as reset target states. States
are called as SNVS and READY. At READY state all the PMIC power outputs go
down and OTP is reload. At the SNVS state all other logic and external
devices apart from the SNVS power domain are shut off. Please refer to NXP
i.MX8 documentation for further information regarding SNVS state. When a
reset is done via SNVS state the PMIC OTP data is not reload. This causes
power outputs that have been under SW control to stay down when reset has
switched power state to SNVS. If reset is done via READY state the power
outputs will be returned to HW control by OTP loading. Thus the reset
target state is set to READY by default. If SNVS state is used the boot
crucial regulators must have the regulator-always-on and regulator-boot-on
properties set in regulator node.
Example:
......@@ -43,6 +57,7 @@ Example:
#clock-cells = <0>;
clocks = <&osc 0>;
clock-output-names = "bd71837-32k-out";
rohm,reset-snvs-powered;
regulators {
buck1: BUCK1 {
......@@ -50,8 +65,10 @@ Example:
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
// [...]
};
};
......
......@@ -27,8 +27,38 @@ BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6
LDO1, LDO2, LDO3, LDO4, LDO5, LDO6
Optional properties:
- rohm,dvs-run-voltage : PMIC default "RUN" state voltage in uV.
See below table for bucks which support this.
- rohm,dvs-idle-voltage : PMIC default "IDLE" state voltage in uV.
See below table for bucks which support this.
- rohm,dvs-suspend-voltage : PMIC default "SUSPEND" state voltage in uV.
See below table for bucks which support this.
- Any optional property defined in bindings/regulator/regulator.txt
Supported default DVS states:
BD71837:
buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage
-----------------------------------------------------------------------------
1 | supported | supported | supported
----------------------------------------------------------------------------
2 | supported | supported | not supported
----------------------------------------------------------------------------
3 | supported | not supported | not supported
----------------------------------------------------------------------------
4 | supported | not supported | not supported
----------------------------------------------------------------------------
rest | not supported | not supported | not supported
BD71847:
buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage
-----------------------------------------------------------------------------
1 | supported | supported | supported
----------------------------------------------------------------------------
2 | supported | supported | not supported
----------------------------------------------------------------------------
rest | not supported | not supported | not supported
Example:
regulators {
buck1: BUCK1 {
......@@ -36,7 +66,11 @@ regulators {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
......@@ -45,18 +79,22 @@ regulators {
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
......
......@@ -20,3 +20,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
/*
* Copyright 2018 Purism SPC
*
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include "dt-bindings/usb/pd.h"
/ {
model = "Purism Librem 5 devkit 1.0";
compatible = "fsl,librem5-devkit", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_pwr_en: pwr_en {
compatible = "regulator-fixed";
regulator-name = "PWR_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
wifi_pwr_en: wifi_en {
compatible = "regulator-fixed";
regulator-name = "WIFI_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
pmic_osc: pmic_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
phy-supply = <&reg_pwr_en>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
power-supply = <&reg_pwr_en>;
};
};
};
&iomuxc {
imx8m-som {
pinctrl_nc: ncgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_up: upgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11 /* CSI_nRST */
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* CSI_PWDN */
MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19 /* CLK01 */
>;
};
pinctrl_pwr_en: pwr_engrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
>;
};
pinctrl_wwan: wwan_grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
>;
};
pinctrl_dsi: dsigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000003f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000003f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000003f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000003f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000003f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000003f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
>;
};
pinctrl_bt: btgrp {
fsl,pins = <
/* BT_REG_ON */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
>;
};
pinctrl_modem_reset: modem_reset {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* nWIFI_RESET */
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 /* nWIFI_DISABLE */
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
>;
};
pinctrl_sai6: sai6grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
>;
};
pinctrl_micsel: micselgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* mic sel */
>;
};
pinctrl_haptic: hapticgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0xc6 /* nHAPTIC */
>;
};
pinctrl_mute: mute {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x86 /* MUTE */
>;
};
pinctrl_pwm4: pwm4 {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0xc6
>;
};
pinctrl_prox: prox_nint {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80
>;
};
pinctrl_charger: charger_nirq {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */
>;
};
pinctrl_rtc: rtcirq {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80
>;
};
pinctrl_pmic: pmic_int {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80
>;
};
pinctrl_spi1: spi1 {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0f
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0f
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0f
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x09
>;
};
pinctrl_imu: imugrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x80 /* IMU_INT */
>;
};
pinctrl_gpio_leds: gpioleds {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
>;
};
pinctrl_gpio_keys: gpiokeys {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */
>;
};
pinctrl_goodix_ts: gt5688 {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: bd71837@4b {
reg = <0x4b>;
compatible = "rohm,bd71837";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
clocks = <&pmic_osc>;
clock-names = "osc";
clock-output-names = "pmic_clk";
rohm,reset-snvs-powered;
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
interrupt-names = "irq";
gpo {
rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
};
regulators {
#address-cells = <1>;
#size-cells = <0>;
buck1_reg: BUCK1 {
reg = <0>;
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2_reg: BUCK2 {
reg = <1>;
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 {
reg = <2>;
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck4_reg: BUCK4 {
reg = <3>;
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck5_reg: BUCK5 {
reg = <4>;
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
reg = <5>;
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck7_reg: BUCK7 {
reg = <6>;
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck8_reg: BUCK8 {
reg = <7>;
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
reg = <8>;
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
reg = <9>;
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
reg = <10>;
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
reg = <11>;
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: LDO5 {
reg = <12>;
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: LDO6 {
reg = <13>;
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo7_reg: LDO7 {
reg = <14>;
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
typec_ptn5100: ptn5110@52 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x52>;
interrupt-parent = <&gpio3>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ss-sel-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 12000, 2000)>;
op-sink-microwatt = <10000000>;
//init-vbus-sink;
//init-vbus-source;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&typec_hs>;
};
};
port@1 {
reg = <1>;
usb_con_ss: endpoint {
remote-endpoint = <&typec_ss>;
};
};
};
};
};
charger: charger@6b { /* bq25896 */
compatible = "ti,bq25890";
reg = <0x6b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_charger>;
interrupt-parent = <&gpio3>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
ti,battery-regulation-voltage = <4192000>; // 4.192V
ti,charge-current = <1600000>; // 1.6 A
ti,termination-current = <66000>; // 66mA
ti,precharge-current = <1300000>; // 1.3A
ti,minimum-sys-voltage = <2750000>; // 2.75V
ti,boost-voltage = <5000000>; // 5V
ti,boost-max-current = <50000>; // 50mA
};
rtc@68 {
pinctrl-names = "default";
compatible = "microcrystal,rv4162";
reg = <0x68>;
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "disabled";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
status = "okay";
lsm9d: lsm9d@6a {
compatible = "st,lsm9ds1-gyro";
reg = <0x6a>;
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&reg_pwr_en>;
};
};
&usb3_phy0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_hs: endpoint {
remote-endpoint = <&usb_con_hs>;
};
};
port@1 {
reg = <1>;
typec_ss: endpoint {
remote-endpoint = <&usb_con_ss>;
};
};
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
extcon = <&typec_ptn5100>;
dr_mode = "otg";
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
fsl,uart-has-rtscts;
/* resets = <&modem_reset>; */
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
power-supply = <&wifi_pwr_en>;
non-removable;
disable-wp;
cap-sdio-irq;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
......@@ -7,6 +7,7 @@
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
......@@ -86,6 +87,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
#cooling-cells = <2>;
};
A53_1: cpu@1 {
......@@ -199,6 +201,88 @@
#interrupt-cells = <2>;
};
tmu: tmu@30260000 {
compatible = "fsl,imx8mq-tmu";
reg = <0x30260000 0x10000>;
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration = <0x00000000 0x00000023
0x00000001 0x00000029
0x00000002 0x0000002f
0x00000003 0x00000035
0x00000004 0x0000003d
0x00000005 0x00000043
0x00000006 0x0000004b
0x00000007 0x00000051
0x00000008 0x00000057
0x00000009 0x0000005f
0x0000000a 0x00000067
0x0000000b 0x0000006f
0x00010000 0x0000001b
0x00010001 0x00000023
0x00010002 0x0000002b
0x00010003 0x00000033
0x00010004 0x0000003b
0x00010005 0x00000043
0x00010006 0x0000004b
0x00010007 0x00000055
0x00010008 0x0000005d
0x00010009 0x00000067
0x0001000a 0x00000070
0x00020000 0x00000017
0x00020001 0x00000023
0x00020002 0x0000002d
0x00020003 0x00000037
0x00020004 0x00000041
0x00020005 0x0000004b
0x00020006 0x00000057
0x00020007 0x00000063
0x00020008 0x0000006f
0x00030000 0x00000015
0x00030001 0x00000021
0x00030002 0x0000002d
0x00030003 0x00000039
0x00030004 0x00000045
0x00030005 0x00000053
0x00030006 0x0000005f
0x00030007 0x00000071>;
#thermal-sensor-cells = <0>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu>;
trips {
cpu_alert0: trip0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
......@@ -413,4 +497,95 @@
interrupt-parent = <&gic>;
};
};
usb3_phy0: phy0@381f0040 {
compatible = "fsl,imx8mq-usb-phy";
#phy-cells = <1>;
reg = <0x0 0x381f0040 0x0 0x40>;
clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
usb3_0: usb0@38100000 {
compatible = "fsl,imx8mq-dwc3";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x38100000 0x0 0x38100000 0x0 0x10000>;
clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
<&clk IMX8MQ_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
<&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <500000000>, <100000000>;
status = "disabled";
usb_dwc3_0: dwc3 {
compatible = "snps,dwc3";
reg = <0x0 0x38100000 0x0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* TODO: check these clock assignments */
clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
<&clk IMX8MQ_CLK_USB_BUS>,
<&clk IMX8MQ_CLK_USB_CORE_REF>;
clock-names = "ref", "bus_early", "suspend";
phys = <&usb3_phy0 0>, <&usb3_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
snps,power-down-scale = <2>;
usb3-resume-missing-cas;
usb3-lpm-capable;
status = "disabled";
};
};
usb3_phy1: phy1@382f0040 {
compatible = "fsl,imx8mq-usb-phy";
#phy-cells = <1>;
reg = <0x0 0x382f0040 0x0 0x40>;
clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
usb3_1: usb1@38200000 {
compatible = "fsl,imx8mq-dwc3";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x38200000 0x0 0x38200000 0x0 0x10000>;
clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
clock-names = "usb2_ctrl_root_clk";
assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
<&clk IMX8MQ_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
<&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <500000000>, <100000000>;
status = "disabled";
usb_dwc3_1: dwc3 {
compatible = "snps,dwc3";
reg = <0x0 0x38200000 0x0 0x10000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* TODO: check these clock assignments */
clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
<&clk IMX8MQ_CLK_USB_BUS>,
<&clk IMX8MQ_CLK_USB_CORE_REF>;
clock-names = "ref", "bus_early", "suspend";
phys = <&usb3_phy1 0>, <&usb3_phy1 1>;
phy-names = "usb2-phy", "usb3-phy";
snps,power-down-scale = <2>;
usb3-resume-missing-cas;
usb3-lpm-capable;
status = "disabled";
};
};
};
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -5,15 +5,14 @@ config WLAN_VENDOR_RSI
If you have a wireless card belonging to this class, say Y.
Note that the answer to this question doesn't directly affect the
kernel: saying N will just cause the configurator to skip all the
questions about these cards. If you say Y, you will be asked for
kernel: saying N will just cause the configurator to skip all
the questions about cards. If you say Y, you will be asked for
your specific card in the following questions.
if WLAN_VENDOR_RSI
config RSI_91X
tristate "Redpine Signals Inc 91x WLAN driver support"
select BT_HCIRSI if RSI_COEX
depends on MAC80211
---help---
This option enabes support for RSI 1x1 devices.
......@@ -25,7 +24,7 @@ config RSI_DEBUGFS
default y
---help---
Say Y, if you would like to enable debug support. This option
creates debugfs entries
creates debugfs entries.
config RSI_SDIO
tristate "Redpine Signals SDIO bus support"
......@@ -43,14 +42,68 @@ config RSI_USB
This option enables the USB bus support in rsi drivers.
Select M (recommended), if you have a RSI 1x1 wireless module.
config RSI_COEX
bool "Redpine Signals WLAN BT Coexistence support"
depends on BT && RSI_91X
depends on !(BT=m && RSI_91X=y)
default y
config RSI_BT_ALONE
bool "Redpine Signals BT alone (classic/LE) mode support"
depends on RSI_91X
default n
---help---
This option enables the BT classic alone upport in rsi drivers.
Say Y, if you want to use this feature.
config RSI_COEX_MODE
bool "Redpine Signals Wi-Fi BT Coex support"
depends on RSI_91X
default n
---help---
This option enables the Wi-Fi BT coex support in rsi drivers.
Select Y, if you have to use this feature.
config RSI_WOW
bool "Redpine Signals WoWLAN support"
depends on RSI_91X
default n
---help---
This option enables the WoWLAN support.
Say Y if you want to use this feature.
config RSI_P2P
bool "Redpine Signals Wi-Fi Direct support"
depends on RSI_91X
default n
---help---
This option enables the Wi-Fi Direct support in rsi drivers.
Select Y, if you have to use this feature.
config HW_SCAN_OFFLOAD
bool "Redpine Signals Hardware scan offload feature"
depends on RSI_91X
default n
---help---
This option enables the hardware scan offload option in rsi drivers.
Select Y, if you have to use this feature.
config CARACALLA_BOARD
bool "Redpine device support on Caracalla board"
depends on RSI_91X
default n
---help---
This option is used to support Caracalla board with RSI driver.
Select Y, if you have to use this support.
config RSI_ZIGB
bool "Redpine device support on Zigbee"
depends on RSI_91X && RSI_COEX_MODE
default n
---help---
This option is used to support Zigbee with RSI driver.
Select Y, if you have to use this support.
config RSI_PURISM
bool "Redpine Signals PURISM FW support"
depends on RSI_91X && RSI_COEX_MODE
default n
---help---
This option enables the WLAN BT coex support in rsi drivers.
Select M (recommended), if you have want to use this feature
and you have RS9113 module.
This option enables the PURISM FW support.
Say Y if you want to use this feature.
endif # WLAN_VENDOR_RSI
# SPDX-License-Identifier: GPL-2.0
#/*
# Copyright (c) 2017 Redpine Signals Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#*/
rsi_91x-y += rsi_91x_main.o
rsi_91x-y += rsi_91x_core.o
rsi_91x-y += rsi_91x_mac80211.o
rsi_91x-y += rsi_91x_mgmt.o
rsi_91x-y += rsi_91x_hal.o
rsi_91x-y += rsi_91x_ps.o
rsi_91x-$(CONFIG_RSI_COEX) += rsi_91x_coex.o
rsi_91x-$(CONFIG_RSI_DEBUGFS) += rsi_91x_debugfs.o
rsi_91x-$(CONFIG_RSI_BT_ALONE) += rsi_91x_hci.o
rsi_91x-$(CONFIG_RSI_COEX_MODE) += rsi_91x_coex.o
rsi_91x-$(CONFIG_RSI_COEX_MODE) += rsi_91x_hci.o
rsi_91x-$(CONFIG_RSI_ZIGB) += rsi_91x_zigb.o
rsi_91x-$(CONFIG_RSI_11K) += rsi_91x_rrm.o
rsi_usb-y += rsi_91x_usb.o rsi_91x_usb_ops.o
rsi_sdio-y += rsi_91x_sdio.o rsi_91x_sdio_ops.o
rsi_usb-$(CONFIG_RSI_USB) += rsi_91x_usb.o rsi_91x_usb_ops.o
rsi_sdio-$(CONFIG_RSI_SDIO) += rsi_91x_sdio.o rsi_91x_sdio_ops.o
obj-$(CONFIG_RSI_91X) += rsi_91x.o
obj-$(CONFIG_RSI_SDIO) += rsi_sdio.o
obj-$(CONFIG_RSI_USB) += rsi_usb.o
/**
* Copyright (c) 2018 Redpine Signals Inc.
/*
* Copyright (c) 2017 Redpine Signals Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "rsi_main.h"
#include "rsi_coex.h"
#include "rsi_mgmt.h"
#include "rsi_hal.h"
#include "rsi_mgmt.h"
static enum rsi_coex_queues rsi_coex_determine_coex_q
(struct rsi_coex_ctrl_block *coex_cb)
static u8 rsi_coex_determine_coex_q(struct rsi_coex_ctrl_block *coex_cb)
{
enum rsi_coex_queues q_num = RSI_COEX_Q_INVALID;
if (skb_queue_len(&coex_cb->coex_tx_qs[RSI_COEX_Q_COMMON]) > 0)
q_num = RSI_COEX_Q_COMMON;
if (skb_queue_len(&coex_cb->coex_tx_qs[RSI_COEX_Q_BT]) > 0)
q_num = RSI_COEX_Q_BT;
if (skb_queue_len(&coex_cb->coex_tx_qs[RSI_COEX_Q_WLAN]) > 0)
q_num = RSI_COEX_Q_WLAN;
u8 q_num = INVALID_QUEUE;
if (skb_queue_len(&coex_cb->coex_tx_qs[VIP_Q]) > 0)
q_num = VIP_Q;
if (skb_queue_len(&coex_cb->coex_tx_qs[COEX_Q]) > 0)
q_num = COEX_Q;
if (skb_queue_len(&coex_cb->coex_tx_qs[BT_Q]) > 0)
q_num = BT_Q;
if (skb_queue_len(&coex_cb->coex_tx_qs[ZIGB_Q]) > 0)
q_num = ZIGB_Q;
if (skb_queue_len(&coex_cb->coex_tx_qs[WLAN_Q]) > 0)
q_num = WLAN_Q;
return q_num;
}
static void rsi_coex_sched_tx_pkts(struct rsi_coex_ctrl_block *coex_cb)
{
enum rsi_coex_queues coex_q = RSI_COEX_Q_INVALID;
u8 coex_q;
struct sk_buff *skb;
do {
#ifdef CONFIG_RSI_ZIGB
struct rsi_common *common = coex_cb->priv;
#endif
while (1) {
coex_q = rsi_coex_determine_coex_q(coex_cb);
rsi_dbg(INFO_ZONE, "queue = %d\n", coex_q);
if (coex_q == RSI_COEX_Q_BT) {
skb = skb_dequeue(&coex_cb->coex_tx_qs[RSI_COEX_Q_BT]);
rsi_send_bt_pkt(coex_cb->priv, skb);
if (coex_q == INVALID_QUEUE) {
rsi_dbg(DATA_TX_ZONE, "No more pkt\n");
break;
}
if ((coex_q == BT_Q) || (coex_q == ZIGB_Q)) {
skb = skb_dequeue(&coex_cb->coex_tx_qs[BT_Q]);
#ifdef CONFIG_RSI_ZIGB
if (common->zb_fsm_state == ZB_DEVICE_READY) {
rsi_dbg(DATA_TX_ZONE, "Sending zigbee pkt\n");
rsi_send_zb_pkt(coex_cb->priv, skb);
} else {
#endif
rsi_dbg(DATA_TX_ZONE, "Sending BT pkt\n");
rsi_send_bt_pkt(coex_cb->priv, skb);
#ifdef CONFIG_RSI_ZIGB
}
#endif
}
} while (coex_q != RSI_COEX_Q_INVALID);
}
}
/**
* rsi_coex_scheduler_thread() - This function is a kernel thread to schedule
* the coex packets to device
* @common: Pointer to the driver private structure.
*
* Return: None.
*/
static void rsi_coex_scheduler_thread(struct rsi_common *common)
{
int status = 0;
struct rsi_coex_ctrl_block *coex_cb =
(struct rsi_coex_ctrl_block *)common->coex_cb;
u32 timeout = EVENT_WAIT_FOREVER;
do {
rsi_wait_event(&coex_cb->coex_tx_thread.event, timeout);
status = rsi_wait_event(&coex_cb->coex_tx_thread.event, timeout);
if (status < 0)
break;
rsi_reset_event(&coex_cb->coex_tx_thread.event);
rsi_coex_sched_tx_pkts(coex_cb);
......@@ -68,59 +113,38 @@ static void rsi_coex_scheduler_thread(struct rsi_common *common)
int rsi_coex_recv_pkt(struct rsi_common *common, u8 *msg)
{
u8 msg_type = msg[RSI_RX_DESC_MSG_TYPE_OFFSET];
u16 msg_type = msg[2];
switch (msg_type) {
case COMMON_CARD_READY_IND:
rsi_dbg(INFO_ZONE, "common card ready received\n");
if (msg_type == COMMON_CARD_READY_IND) {
common->hibernate_resume = false;
rsi_dbg(INFO_ZONE, "COMMON CARD READY RECEIVED\n");
rsi_handle_card_ready(common, msg);
break;
case SLEEP_NOTIFY_IND:
rsi_dbg(INFO_ZONE, "sleep notify received\n");
} else if (msg_type == SLEEP_NOTIFY_IND) {
rsi_dbg(INFO_ZONE, "\n\n sleep notify RECEIVED\n");
rsi_mgmt_pkt_recv(common, msg);
break;
}
return 0;
}
static inline int rsi_map_coex_q(u8 hal_queue)
{
switch (hal_queue) {
case RSI_COEX_Q:
return RSI_COEX_Q_COMMON;
case RSI_WLAN_Q:
return RSI_COEX_Q_WLAN;
case RSI_BT_Q:
return RSI_COEX_Q_BT;
}
return RSI_COEX_Q_INVALID;
}
int rsi_coex_send_pkt(void *priv, struct sk_buff *skb, u8 hal_queue)
int rsi_coex_send_pkt(void *priv,
struct sk_buff *skb,
u8 hal_queue)
{
struct rsi_common *common = (struct rsi_common *)priv;
struct rsi_coex_ctrl_block *coex_cb =
(struct rsi_coex_ctrl_block *)common->coex_cb;
struct skb_info *tx_params = NULL;
enum rsi_coex_queues coex_q;
int status;
int status = 0;
coex_q = rsi_map_coex_q(hal_queue);
if (coex_q == RSI_COEX_Q_INVALID) {
rsi_dbg(ERR_ZONE, "Invalid coex queue\n");
return -EINVAL;
}
if (coex_q != RSI_COEX_Q_COMMON &&
coex_q != RSI_COEX_Q_WLAN) {
skb_queue_tail(&coex_cb->coex_tx_qs[coex_q], skb);
/* Add pkt to queue if not WLAN packet */
if (hal_queue != RSI_WLAN_Q) {
skb_queue_tail(&coex_cb->coex_tx_qs[hal_queue], skb);
rsi_set_event(&coex_cb->coex_tx_thread.event);
return 0;
return status;
}
if (common->iface_down) {
tx_params =
(struct skb_info *)&IEEE80211_SKB_CB(skb)->driver_data;
tx_params = (struct skb_info *)&IEEE80211_SKB_CB(skb)->driver_data;
if (!(tx_params->flags & INTERNAL_MGMT_PKT)) {
rsi_indicate_tx_status(common->priv, skb, -EINVAL);
......@@ -134,12 +158,12 @@ int rsi_coex_send_pkt(void *priv, struct sk_buff *skb, u8 hal_queue)
else
status = rsi_send_data_pkt(common, skb);
return status;
return 0;
}
int rsi_coex_attach(struct rsi_common *common)
int rsi_coex_init(struct rsi_common *common)
{
struct rsi_coex_ctrl_block *coex_cb;
struct rsi_coex_ctrl_block *coex_cb = NULL;
int cnt;
coex_cb = kzalloc(sizeof(*coex_cb), GFP_KERNEL);
......@@ -148,6 +172,7 @@ int rsi_coex_attach(struct rsi_common *common)
common->coex_cb = (void *)coex_cb;
coex_cb->priv = common;
sema_init(&coex_cb->tx_bus_lock, 1);
/* Initialize co-ex queues */
for (cnt = 0; cnt < NUM_COEX_TX_QUEUES; cnt++)
......@@ -160,21 +185,28 @@ int rsi_coex_attach(struct rsi_common *common)
rsi_coex_scheduler_thread,
"Coex-Tx-Thread")) {
rsi_dbg(ERR_ZONE, "%s: Unable to init tx thrd\n", __func__);
return -EINVAL;
goto err;