librem5.dts 10 KB
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/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
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 * Copyright (C) 2019 Purism SPC
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 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/dts-v1/;

#include "fsl-imx8mq.dtsi"

/ {
	model = "Librem 5";
	compatible = "purism,librem5", "fsl,imx8mq";

	chosen {
		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
		stdout-path = &uart1;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;
		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "VSD_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};

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	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pinctrl_led>;
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		ledr {
			label = "LED_R";
			gpios = <&gpio5 3 0>;
		};
		ledg {
			label = "LED_G";
			gpios = <&gpio5 2 0>;
		};
		ledb {
			label = "LED_B";
			gpios = <&gpio1 13 0>;
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		};
	};
};

&iomuxc {
	pinctrl-names = "default";
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	pinctrl-0 = <&pinctrl_hog>;

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	imx8m-som {
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		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x3f
				MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x3f
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				MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16		0xC0
				MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17		0xC0
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				MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x3f
				MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x3f
				MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x3f
				MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x3f
				MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x3f
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				MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x83 /* 4G_PWR_EN */
				MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x83 /* HUB_PWR_3V3_EN */
				MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x3 /* CHG_EN */
				MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x3 /* CHG_OTG_OUT_EN */
				MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x83 /* WIFI3V3_EN */
				MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x83 /* GPS3V3_EN */
				MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x83 /* BACKLINGE_EN */
				MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x83 /*	TF_PWR_3V3_EN */
				MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x83 /*	AUDIO_POWER_EN_3V3 */
				MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x83 /*	DSI_EN_3V3 */
				MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20		0x83 /*	DSI_BIAS_EN */
				MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23		0x83 /*	FLASH_EN */
				MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x83 /*	CAMERA_PWR_EN_3V3 */
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			>;
		};

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		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
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				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000026
				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000026
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			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
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				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000026
				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000026
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			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
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				MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000026
				MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000026
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			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
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				MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000026
				MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000026
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			>;
		};

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		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
				MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9   0x82
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
			>;
		};

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		pinctrl_led: ledgrp {
			fsl,pins = <
				MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3		0x16 /* LED_R */
				MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x16 /* LED_G */
				MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16 /* LED_B */
			>;
		};

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	        pinctrl_pwm1: pwm1grp {
	                fsl,pins = <
				MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT     0x83 /* MOTO */
			>;
		};

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		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79
				MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79
				MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x79
				MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x79
				MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x83
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x8d
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8f
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcf
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcf
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcf
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcf
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcf
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcf
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcf
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcf
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcf
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x8f
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

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                pinctrl_usdhc2_gpio: usdhc2grpgpio {
                        fsl,pins = <
                                MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41    /* WIFI_nRST */
                        >;
                };

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8f
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcf
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcf
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcf
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcf
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcf
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_sai2: sai2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
			>;
		};

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		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
			>;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";
};

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&ecspi1 {
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
 	status = "okay";
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	flash0: winbond@0 {
 		reg = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
		compatible = "spi-flash";
 		spi-max-frequency = <29000000>;
 	};
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};

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&uart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	status = "okay";
};

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#if 0
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&lcdif {
	status = "okay";
	disp-dev = "mipi_dsi_northwest";
	display = <&display0>;

	display0: display@0 {
		bits-per-pixel = <24>;
		bus-width = <24>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
			clock-frequency = <9200000>;
			hactive = <480>;
			vactive = <272>;
			hfront-porch = <8>;
			hback-porch = <4>;
			hsync-len = <41>;
			vback-porch = <2>;
			vfront-porch = <4>;
			vsync-len = <10>;

			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <0>;
			};
		};
	};
};
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#endif
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&uart3 { /* BT */
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	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	fsl,uart-has-rtscts;
	status = "disabled";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

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&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
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	broken-cd;
	//cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
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	status = "okay";
};

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&usb3_phy0 {
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	status = "okay";
	dr_mode = "peripheral";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	status = "okay";
	dr_mode = "host";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};