-
Ye Li authored
8QXP B0 chip already fix the DPLL unstable issue, so we set back the usdhc clock parent to PLL0 (DPLL) for B0 chip. A0 chip will remain use the PLL1 (AVPLL). Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
6e60ea84