Commit 126d2e1a authored by Ye Li's avatar Ye Li
Browse files

MLK-14380-1 mx6ullarm2: Add mx6ull DDR3 ARM2 board codes



Move the mx6ull ddr3 arm2 board codes and defconfigs from v2016.03
as the base for converting to use DTB OF_CONTROL.
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
parent e4f53022
......@@ -285,6 +285,13 @@ config TARGET_MX6UL_GEAM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6ULL_DDR3_ARM2
bool "Support mx6ull_ddr3_arm2"
select BOARD_LATE_INIT
select MX6ULL
select DM
select DM_THERMAL
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
select BOARD_LATE_INIT
......@@ -423,6 +430,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/freescale/mx6ull_ddr3_arm2/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
......
if TARGET_MX6ULL_DDR3_ARM2
config SYS_BOARD
default "mx6ull_ddr3_arm2"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "mx6ull_ddr3_arm2"
endif
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6ull_ddr3_arm2.o
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6ull_ddr3_arm2/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x000C0030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00150019
DATA 4 0x021B083C 0x41550153
DATA 4 0x021B0848 0x40403A3E
DATA 4 0x021B0850 0x40402F2A
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B08C0 0x00944009
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
DATA 4 0x021B000C 0x676B52F3
DATA 4 0x021B0010 0xB66D0B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00211740
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000005F
DATA 4 0x021B0000 0x85180000
DATA 4 0x021B0890 0x00400000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
#endif
This diff is collapsed.
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
/* DDR script */
.macro imx6ull_ddr3_arm2_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x000C0000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
ldr r1, =0x000C0030
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
ldr r1, =0x00000030
str r1, [r0, #0x260]
str r1, [r0, #0x264]
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00000030
str r1, [r0, #0x280]
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00150019
str r1, [r0, #0x80C]
ldr r1, =0x41550153
str r1, [r0, #0x83C]
ldr r1, =0x40403A3E
str r1, [r0, #0x848]
ldr r1, =0x40402F2A
str r1, [r0, #0x850]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x00944009
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x0002002D
str r1, [r0, #0x004]
ldr r1, =0x1B333030
str r1, [r0, #0x008]
ldr r1, =0x676B52F3
str r1, [r0, #0x00C]
ldr r1, =0xB66D0B63
str r1, [r0, #0x010]
ldr r1, =0x01FF00DB
str r1, [r0, #0x014]
ldr r1, =0x00211740
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x000026D2
str r1, [r0, #0x02C]
ldr r1, =0x006B1023
str r1, [r0, #0x030]
ldr r1, =0x0000005F
str r1, [r0, #0x040]
ldr r1, =0x85180000
str r1, [r0, #0x000]
ldr r1, =0x00400000
str r1, [r0, #0x890]
ldr r1, =0x02008032
str r1, [r0, #0x01C]
ldr r1, =0x00008033
str r1, [r0, #0x01C]
ldr r1, =0x00048031
str r1, [r0, #0x01C]
ldr r1, =0x15208030
str r1, [r0, #0x01C]
ldr r1, =0x04008040
str r1, [r0, #0x01C]
ldr r1, =0x00000800
str r1, [r0, #0x020]
ldr r1, =0x00000227
str r1, [r0, #0x818]
ldr r1, =0x0002552D
str r1, [r0, #0x004]
ldr r1, =0x00011006
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6_clock_gating
ldr r0, =CCM_BASE_ADDR
ldr r1, =0xFFFFFFFF
str r1, [r0, #0x68]
str r1, [r0, #0x6C]
str r1, [r0, #0x70]
str r1, [r0, #0x74]
str r1, [r0, #0x78]
str r1, [r0, #0x7C]
str r1, [r0, #0x80]
.endm
.macro imx6_qos_setting
.endm
.macro imx6_ddr_setting
imx6ull_ddr3_arm2_setting
.endm
/* include the common plugin code here */
#include <asm/arch/mx6_plugin.S>
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
CONFIG_CMD_GPIO=y
\ No newline at end of file
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,MX6ULL_DDR3_ARM2_EMMC_REWORK"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
CONFIG_CMD_GPIO=y
\ No newline at end of file
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,SYS_BOOT_NAND"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
CONFIG_CMD_GPIO=y
\ No newline at end of file
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,SYS_BOOT_QSPI"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
CONFIG_CMD_GPIO=y
\ No newline at end of file
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,SYS_BOOT_SPINOR"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
CONFIG_CMD_GPIO=y
\ No newline at end of file
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,MX6ULL_DDR3_ARM2_TSC_REWORK"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
CONFIG_CMD_GPIO=y
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX6ULL_DDR3_ARM2_CONFIG_H
#define __MX6ULL_DDR3_ARM2_CONFIG_H
#define CONFIG_DEFAULT_FDT_FILE "imx6ull-14x14-ddr3-arm2.dtb"
#ifdef CONFIG_SYS_BOOT_QSPI
#define CONFIG_SYS_USE_QSPI
#define CONFIG_ENV_IS_IN_SPI_FLASH
#elif defined CONFIG_SYS_BOOT_SPINOR
#define CONFIG_SYS_USE_SPINOR
#define CONFIG_ENV_IS_IN_SPI_FLASH
#elif defined CONFIG_SYS_BOOT_NAND
#define CONFIG_SYS_USE_NAND
#define CONFIG_ENV_IS_IN_NAND
#else
#ifndef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
#define CONFIG_SYS_USE_QSPI
#endif
#define CONFIG_ENV_IS_IN_MMC
#endif
#define CONFIG_VIDEO
#define CONFIG_FSL_USDHC
#define BOOTARGS_CMA_SIZE ""
#include "mx6ul_arm2.h"
#define CONFIG_IOMUX_LPSR
#define PHYS_SDRAM_SIZE SZ_1G
/*
* TSC pins conflict with I2C1 bus, so after TSC
* hardware rework, need to disable i2c1 bus, also
* need to disable PMIC and ldo bypass check.
*/
#ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK
#undef CONFIG_LDO_BYPASS_CHECK
#undef CONFIG_SYS_I2C_MXC
#undef CONFIG_SYS_I2C
#undef CONFIG_CMD_I2C
#undef CONFIG_POWER_PFUZE100_I2C_ADDR
#undef CONFIG_POWER_PFUZE100
#undef CONFIG_POWER_I2C
#undef CONFIG_POWER
#endif
#ifdef CONFIG_SYS_USE_SPINOR
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#define CONFIG_SF_DEFAULT_CS 0
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x2
#define CONFIG_FEC_XCV_TYPE MII100
#endif
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_FEC_DMA_MINALIGN 64
#endif
#endif
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