MLK-14382-1 mx6ularm2: Add DDR3 and LPDDR2 ARM2 board codes

Move the mx6ul DDR3/LPDDR2 ARM2 boards codes from v2016.03 u-boot as
the base for OF_CONTROL enabling.
Signed-off-by: Ye Li <ye.li@nxp.com>

arch/arm/cpu/armv7/mx6/Kconfig

@@ -259,6 +259,20 @@ config TARGET_MX6UL_14X14_EVK
 	select DM_THERMAL
 	select SUPPORT_SPL
 
+config TARGET_MX6UL_14X14_DDR3_ARM2
+	bool "mx6ul_14x14_ddr3_arm2"
+	select BOARD_LATE_INIT
+	select MX6UL
+	select DM
+	select DM_THERMAL
+
+config TARGET_MX6UL_14X14_LPDDR2_ARM2
+	bool "mx6ul_14x14_lpddr2_arm2"
+	select BOARD_LATE_INIT
+	select MX6UL
+	select DM
+	select DM_THERMAL
+
 config TARGET_MX6UL_GEAM
 	bool "Support Engicam GEAM6UL"
 	select MX6UL
@@ -406,6 +420,8 @@ source "board/freescale/mx6sllevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
+source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
 source "board/freescale/mx6ullevk/Kconfig"
 source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"

board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig

+if TARGET_MX6UL_14X14_DDR3_ARM2
+
+config SYS_BOARD
+       default "mx6ul_14x14_ddr3_arm2"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_CONFIG_NAME
+       default "mx6ul_14x14_ddr3_arm2"
+
+endif

board/freescale/mx6ul_14x14_ddr3_arm2/Makefile

+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ul_14x14_ddr3_arm2.o

board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg

+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x0013000F
+DATA 4 0x021B083C 0x415D0159
+DATA 4 0x021B0848 0x4040484F
+DATA 4 0x021B0850 0x40405247
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00922012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333000
+DATA 4 0x021B000C 0x676B54B3
+DATA 4 0x021B0010 0xB68E0A83
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00211740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0x85180000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif

board/freescale/mx6ul_14x14_ddr3_arm2/plugin.S

+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ul_ddr3_arm2_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0013000F
+	str r1, [r0, #0x80C]
+	ldr r1, =0x415D0159
+	str r1, [r0, #0x83C]
+	ldr r1, =0x4040484F
+	str r1, [r0, #0x848]
+	ldr r1, =0x40405247
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00922012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x1B333000
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B54B3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB68E0A83
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00211740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0x85180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+	str r1, [r0, #0x84]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ul_ddr3_arm2_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>

board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig

+if TARGET_MX6UL_14X14_LPDDR2_ARM2
+
+config SYS_BOARD
+       default "mx6ul_14x14_lpddr2_arm2"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_CONFIG_NAME
+       default "mx6ul_14x14_lpddr2_arm2"
+
+endif

board/freescale/mx6ul_14x14_lpddr2_arm2/Makefile

+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ul_14x14_lpddr2_arm2.o

board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg

+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020E04B4 0x00080000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000028
+DATA 4 0x020E0250 0x00000028
+DATA 4 0x020E024C 0x00000028
+DATA 4 0x020E0490 0x00000028
+DATA 4 0x020E0288 0x00000028
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000000
+DATA 4 0x020E0264 0x00000000
+DATA 4 0x020E04A0 0x00000028
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00003028
+DATA 4 0x020E0284 0x00003028
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000028
+DATA 4 0x020E04A4 0x00000028
+DATA 4 0x020E0244 0x00000028
+DATA 4 0x020E0248 0x00000028
+
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B085C 0x1b4700c7
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0890 0x00470000
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B083C 0x20000000
+DATA 4 0x021B0848 0x4040484F
+DATA 4 0x021B0850 0x40405247
+DATA 4 0x021B08C0 0x00922012
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020012
+DATA 4 0x021B0008 0x00000000
+DATA 4 0x021B000C 0x33374133
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170557
+DATA 4 0x021B0014 0x00000093
+DATA 4 0x021B0018 0x00001748
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x0F9F0682
+DATA 4 0x021B0030 0x009F0010
+DATA 4 0x021B0040 0x00000047
+DATA 4 0x021B0000 0x83100000
+DATA 4 0x021B001C 0x00008010
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0818 0x00000000
+DATA 4 0x021B0800 0xA1310003
+DATA 4 0x021B0004 0x00025576
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif

board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.S

+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ul_lpddr2_arm2_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00003028
+	str r1, [r0, #0x280]
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0x1b4700c7
+	str r1, [r0, #0x5C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00470000
+	str r1, [r0, #0x890]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+	ldr r1, =0x4040484F
+	str r1, [r0, #0x848]
+	ldr r1, =0x40405247
+	str r1, [r0, #0x850]
+	ldr r1, =0x00922012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020012
+	str r1, [r0, #0x004]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x008]
+	ldr r1, =0x33374133
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170557
+	str r1, [r0, #0x038]
+	ldr r1, =0x00000093
+	str r1, [r0, #0x014]
+	ldr r1, =0x00001748
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x0F9F0682
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0010
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0x83100000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00008010
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x818]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00025576
+	str r1, [r0, #0x004]
+	ldr r1, =0x00010106
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+	str r1, [r0, #0x84]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ul_lpddr2_arm2_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>

configs/mx6ul_14x14_ddr3_arm2_defconfig

+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg"
+CONFIG_CMD_GPIO=y