Commit 889fef96 authored by Ye Li's avatar Ye Li Committed by Jason Liu
Browse files

MLK-16724 imx8mq: clock: Fix FRAC PLL caculation issue



According to the FRAC PLL formula, DIVF_VAL = 1 + DIVFI + (DIVFF/224).
But in decode_frac_pll, the DIVFI and DIVFF are both added with 1. Fix it to
align with the formula.
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
parent 2dd49234
......@@ -82,7 +82,7 @@ u32 decode_frac_pll(enum clk_root_src frac_pll)
FRAC_PLL_FRAC_DIV_CTL_SHIFT;
divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
divf_val = 1 + (divfi + 1) + (divff + 1) / (1 << 24);
divf_val = 1 + divfi + divff / (1 << 24);
pllout = pll_refclk / (divr_val + 1) * 8 * divf_val / ((divq_val + 1) * 2);
......
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