imx8m: Add Purism Librem5 devkit board

This commit creates a new board for the Purism Librem5 devkit.

- The board code was copied from the emcraft/imx8m_som board, minus the
parts which were not relevant (other DDR configs).
- The Emcraft-specific preprocessor defines have been removed.
- A new librem5.h configuration file was created.

arch/arm/cpu/armv8/imx8m/Kconfig

@@ -90,6 +90,12 @@ config TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
 
 endchoice
 
+config TARGET_PURISM_LIBREM5_DEVKIT
+	bool "Purism Librem5 devkit"
+	select IMX8M
+	select IMX8MQ
+	select SUPPORT_SPL
+
 config SYS_SOC
 	default "imx8m"
 
@@ -99,5 +105,6 @@ source "board/freescale/imx8mq_arm2/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
 source "board/freescale/imx8mm_val/Kconfig"
 source "board/emcraft/imx8m_som/Kconfig"
+source "board/purism/librem5/Kconfig"
 
 endif

board/purism/common

+../freescale/common
\ No newline at end of file

board/purism/librem5/Kconfig

+if TARGET_PURISM_LIBREM5_DEVKIT
+
+config SYS_BOARD
+	default "librem5"
+
+config SYS_VENDOR
+	default "purism"
+
+config SYS_CONFIG_NAME
+	default "librem5"
+
+config M4_LOAD_DDR_TRAINING
+	bool "Use the M4 to load the DDR training firmware"
+
+endif

board/purism/librem5/Makefile

+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8m_som.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/lpddr4_3gb/ddr_init.o ddr/lpddr4_3gb/ddrphy_train.o \
+	 ddr/lpddr4_3gb/helper.o
+endif

board/purism/librem5/ddr/lpddr4_3gb/ddr.h

+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+enum fw_type {
+	FW_1D_IMAGE,
+	FW_2D_IMAGE,
+};
+
+void ddr_init(void);
+void ddr_load_train_code(enum fw_type type);
+void lpddr4_800M_cfg_phy(void);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+	writel(val, addr);
+}
+
+static inline uint32_t reg32_read(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
+{
+    writel(val, addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+	setbits_le32(addr, (1 << bit));
+}

board/purism/librem5/ddr/lpddr4_3gb/ddr_init.c

+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr_memory_map.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "wait_ddrphy_training_complete.c"
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+#define SILICON_TRAIN
+
+void ddr_cfg_phy(void);
+volatile unsigned int tmp, tmp_t, i;
+void ddr_init(void)
+{
+	/** Initialize DDR clock and DDRC registers **/
+	reg32_write(0x3038a088,0x7070000);
+	reg32_write(0x3038a084,0x4030000);
+	reg32_write(0x303a00ec,0xffff);
+	tmp=reg32_read(0x303a00f8);
+	tmp |= 0x20;
+	reg32_write(0x303a00f8,tmp);
+	reg32_write(0x30391000,0x8f000000);
+	reg32_write(0x30391004,0x8f000000);
+	reg32_write(0x30360068,0xece580);
+	tmp=reg32_read(0x30360060);
+	tmp &= ~0x80;
+	reg32_write(0x30360060,tmp);
+	tmp=reg32_read(0x30360060);
+	tmp |= 0x200;
+	reg32_write(0x30360060,tmp);
+	tmp=reg32_read(0x30360060);
+	tmp &= ~0x20;
+	reg32_write(0x30360060,tmp);
+	tmp=reg32_read(0x30360060);
+	tmp &= ~0x10;
+	reg32_write(0x30360060,tmp);
+	do{
+		tmp=reg32_read(0x30360060);
+		if(tmp&0x80000000) break;
+	}while(1);
+	reg32_write(0x30391000,0x8f000006);
+	reg32_write(0x3d400304,0x1);
+	reg32_write(0x3d400030,0x1);
+	reg32_write(0x3d400000,0xa3080020);
+	reg32_write(0x3d400028,0x0);
+	reg32_write(0x3d400020,0x203);
+	reg32_write(0x3d400024,0x186a000);
+	reg32_write(0x3d400064,0x6100e0);
+	reg32_write(0x3d4000d0,0xc003061c);
+	reg32_write(0x3d4000d4,0x9e0000);
+	reg32_write(0x3d4000dc,0xd4002d);
+	reg32_write(0x3d4000e0,0x310008);
+	reg32_write(0x3d4000e8,0x66004a);
+	reg32_write(0x3d4000ec,0x16004a);
+	reg32_write(0x3d400100,0x1a201b22);
+	reg32_write(0x3d400104,0x60633);
+	reg32_write(0x3d40010c,0xc0c000);
+	reg32_write(0x3d400110,0xf04080f);
+	reg32_write(0x3d400114,0x2040c0c);
+	reg32_write(0x3d400118,0x1010007);
+	reg32_write(0x3d40011c,0x401);
+	reg32_write(0x3d400130,0x20600);
+	reg32_write(0x3d400134,0xc100002);
+	reg32_write(0x3d400138,0xe6);
+	reg32_write(0x3d400144,0xa00050);
+	reg32_write(0x3d400180,0x3200018);
+	reg32_write(0x3d400184,0x28061a8);
+	reg32_write(0x3d400188,0x0);
+	reg32_write(0x3d400190,0x497820a);
+	reg32_write(0x3d400194,0x80303);
+	reg32_write(0x3d4001a0,0xe0400018);
+	reg32_write(0x3d4001a4,0xdf00e4);
+	reg32_write(0x3d4001a8,0x80000000);
+	reg32_write(0x3d4001b0,0x11);
+	reg32_write(0x3d4001b4,0x170a);
+	reg32_write(0x3d4001c0,0x1);
+	reg32_write(0x3d4001c4,0x1);
+	reg32_write(0x3d4000f4,0x639);
+	reg32_write(0x3d400108,0x70e1214);
+	reg32_write(0x3d400200,0x15);
+	reg32_write(0x3d40020c,0x0);
+	reg32_write(0x3d400210,0x1f1f);
+	reg32_write(0x3d400204,0x80808);
+	reg32_write(0x3d400214,0x7070707);
+	reg32_write(0x3d400218,0x48080707);
+	reg32_write(0x3d402020,0x1);
+	reg32_write(0x3d402024,0x518b00);
+	reg32_write(0x3d402050,0x20d040);
+	reg32_write(0x3d402064,0x14002f);
+	reg32_write(0x3d4020dc,0x940009);
+	reg32_write(0x3d4020e0,0x310000);
+	reg32_write(0x3d4020e8,0x66004a);
+	reg32_write(0x3d4020ec,0x16004a);
+	reg32_write(0x3d402100,0xb070508);
+	reg32_write(0x3d402104,0x3040b);
+	reg32_write(0x3d402108,0x305090c);
+	reg32_write(0x3d40210c,0x505000);
+	reg32_write(0x3d402110,0x4040204);
+	reg32_write(0x3d402114,0x2030303);
+	reg32_write(0x3d402118,0x1010004);
+	reg32_write(0x3d40211c,0x301);
+	reg32_write(0x3d402130,0x20300);
+	reg32_write(0x3d402134,0xa100002);
+	reg32_write(0x3d402138,0x31);
+	reg32_write(0x3d402144,0x220011);
+	reg32_write(0x3d402180,0xa70006);
+	reg32_write(0x3d402190,0x3858202);
+	reg32_write(0x3d402194,0x80303);
+	reg32_write(0x3d4021b4,0x502);
+	reg32_write(0x3d400244,0x0);
+	reg32_write(0x3d400250,0x29001505);
+	reg32_write(0x3d400254,0x2c);
+	reg32_write(0x3d40025c,0x5900575b);
+	reg32_write(0x3d400264,0x9);
+	reg32_write(0x3d40026c,0x2005574);
+	reg32_write(0x3d400300,0x16);
+	reg32_write(0x3d400304,0x0);
+	reg32_write(0x3d40030c,0x0);
+	reg32_write(0x3d400320,0x1);
+	reg32_write(0x3d40036c,0x11);
+	reg32_write(0x3d400400,0x111);
+	reg32_write(0x3d400404,0x10f3);
+	reg32_write(0x3d400408,0x72ff);
+	reg32_write(0x3d400490,0x1);
+	reg32_write(0x3d400494,0x1110d00);
+	reg32_write(0x3d400498,0x620790);
+	reg32_write(0x3d40049c,0x100001);
+	reg32_write(0x3d4004a0,0x41f);
+	reg32_write(0x30391000,0x8f000004);
+	reg32_write(0x30391000,0x8f000000);
+	reg32_write(0x3d400030,0xa8);
+	do{
+		tmp=reg32_read(0x3d400004);
+		if(tmp&0x223) break;
+	}while(1);
+	reg32_write(0x3d400320,0x0);
+	reg32_write(0x3d000000,0x1);
+	reg32_write(0x3d4001b0,0x10);
+	reg32_write(0x3c040280,0x0);
+	reg32_write(0x3c040284,0x1);
+	reg32_write(0x3c040288,0x2);
+	reg32_write(0x3c04028c,0x3);
+	reg32_write(0x3c040290,0x4);
+	reg32_write(0x3c040294,0x5);
+	reg32_write(0x3c040298,0x6);
+	reg32_write(0x3c04029c,0x7);
+	reg32_write(0x3c044280,0x0);
+	reg32_write(0x3c044284,0x1);
+	reg32_write(0x3c044288,0x2);
+	reg32_write(0x3c04428c,0x3);
+	reg32_write(0x3c044290,0x4);
+	reg32_write(0x3c044294,0x5);
+	reg32_write(0x3c044298,0x6);
+	reg32_write(0x3c04429c,0x7);
+	reg32_write(0x3c048280,0x0);
+	reg32_write(0x3c048284,0x1);
+	reg32_write(0x3c048288,0x2);
+	reg32_write(0x3c04828c,0x3);
+	reg32_write(0x3c048290,0x4);
+	reg32_write(0x3c048294,0x5);
+	reg32_write(0x3c048298,0x6);
+	reg32_write(0x3c04829c,0x7);
+	reg32_write(0x3c04c280,0x0);
+	reg32_write(0x3c04c284,0x1);
+	reg32_write(0x3c04c288,0x2);
+	reg32_write(0x3c04c28c,0x3);
+	reg32_write(0x3c04c290,0x4);
+	reg32_write(0x3c04c294,0x5);
+	reg32_write(0x3c04c298,0x6);
+	reg32_write(0x3c04c29c,0x7);
+
+	/* Configure DDR PHY's registers */
+	ddr_cfg_phy();
+
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+	reg32_write(DDRC_SWCTL(0), 0x0000);
+	/*
+	 * ------------------- 9 -------------------
+	 * Set DFIMISC.dfi_init_start to 1 
+	 *  -----------------------------------------
+	 */
+	reg32_write(DDRC_DFIMISC(0), 0x00000030);
+	reg32_write(DDRC_SWCTL(0), 0x0001);
+
+	/* wait DFISTAT.dfi_init_complete to 1 */
+	tmp_t = 0;
+	while(tmp_t==0){
+		tmp  = reg32_read(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+		tmp  = reg32_read(DDRC_MRSTAT(0));
+	}
+
+	reg32_write(DDRC_SWCTL(0), 0x0000);
+
+	/* clear DFIMISC.dfi_init_complete_en */
+	reg32_write(DDRC_DFIMISC(0), 0x00000010);
+	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+	/*
+	 * set SWCTL.sw_done to enable quasi-dynamic register
+	 * programming outside reset.
+	 */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+		;
+
+	/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+	while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+		;
+
+	reg32_write(DDRC_PWRCTL(0), 0x00000088);
+	/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+	/* enable port 0 */
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	/* enable DDR auto-refresh mode */
+	tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
+	reg32_write(DDRC_RFSHCTL3(0), tmp);
+}
\ No newline at end of file

board/purism/librem5/ddr/lpddr4_3gb/helper.c

+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <mmc.h>
+#include <blk.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr_memory_map.h>
+#include <asm/arch/clock.h>
+#include <asm/sections.h>
+#include <asm/arch/sys_proto.h>
+#include <fsl_wdog.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OCRAM_BASE	0x900000
+#define OCRAM_SIZE	(128*1024)
+
+#define TCML_BASE       0x7e0000
+#define TCMU_BASE       0x800000
+#define TCMU_SIZE       0x20000
+#define TCMU_CMD_M4     (TCMU_BASE + TCMU_SIZE - 24) /* command mailbox */
+#define TCMU_ARG_M4     (TCMU_BASE + TCMU_SIZE - 20) /* arg mailbox */
+#define TCMU_ST_M4      (TCMU_BASE + TCMU_SIZE - 16) /* status mailbox */
+#define TCMU_CMD_A53    (TCMU_BASE + TCMU_SIZE - 12) /* command mailbox */
+#define TCMU_ARG_A53    (TCMU_BASE + TCMU_SIZE - 8) /* arg mailbox */
+#define TCMU_ST_A53     (TCMU_BASE + TCMU_SIZE - 4) /* status mailbox */
+
+#define CMD_NONE        0
+#define CMD_READY       1
+#define CMD_WRITE_FW    2
+#define ST_NONE         0
+#define ST_READY        1
+#define ST_FAIL         2
+#define ST_SUCCESS      3
+#define ST_BUSY		4
+#define ST_EXCEPT	5
+
+#define IMEM_LEN 32768//23400	//byte
+#define DMEM_LEN 16384//1720	//byte
+#define IMEM_2D_OFFSET 	49152
+#define FIRMWARE_BASE	(OCRAM_BASE + OCRAM_SIZE / 2)	
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+struct aipstz_regs {
+	u32     mprot0;
+	u32     mprot1;
+	u32     rsvd[0xe];
+	u32     opacr0;
+	u32     opacr1;
+	u32     opacr2;
+	u32     opacr3;
+	u32	opacr4;
+};
+
+/* We need PHY iMEM PHY is 32KB padded */
+void old_ddr_load_train_code(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN; ){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	printf("check ddr4_pmu_train_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+	if(error){
+		printf("check ddr4_pmu_train_imem code fail=%d\n",error);
+	}else{
+		printf("check ddr4_pmu_train_imem code pass\n");
+	}
+
+	printf("check ddr4_pmu_train_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+
+	if(error){
+		printf("check ddr4_pmu_train_dmem code fail=%d",error);
+	}else{
+		printf("check ddr4_pmu_train_dmem code pass\n");
+	}
+}
+
+void load_train_code_tcmu(enum fw_type type)
+{
+	u32 tmp32, i;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	printf("copying ddr4_pmu_train_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = FIRMWARE_BASE;
+	for(i = 0x0; i < IMEM_LEN; ){
+		tmp32 = readl(pr_from32);
+		writel(tmp32, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	printf("copying ddr4_pmu_train_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = FIRMWARE_BASE+IMEM_LEN;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = readl(pr_from32);
+		writel(tmp32, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+}
+
+extern int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
+
+int is_mx8(void)
+{
+	return 1;
+}
+
+void init_aips(void)
+{
+	struct aipstz_regs *aips[4];
+	int num_aips = 2, i;
+
+	aips[0] = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+	aips[1] = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+	aips[2] = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+	aips[3] = (struct aipstz_regs *)AIPS4_BASE_ADDR;
+
+	if (is_mx6ull() || is_mx6sx() || is_mx7())
+		num_aips = 3;
+
+	if(is_mx8())
+		num_aips = 4;
+
+	for( i=0; i<num_aips; i++) {
+		/*
+		 * Set all MPROTx to be non-bufferable, trusted for R/W,
+		 * not forced to user-mode.
+		 */
+		writel(0x77770700, &aips[i]->mprot0);
+		//writel(0x77777777, &aips[i]->mprot1);
+
+		/*
+		 * Set all OPACRx to be non-bufferable, not require
+		 * supervisor privilege level for access,allow for
+		 * write access and untrusted master access.
+		 */
+		writel(0x00000000, &aips[i]->opacr0);
+		writel(0x00000000, &aips[i]->opacr1);
+		writel(0x00000000, &aips[i]->opacr2);
+		writel(0x00000000, &aips[i]->opacr3);
+		writel(0x00000000, &aips[i]->opacr4);
+	}
+}
+
+#define SRC_M4RCR 0x3039000C
+
+void M4_load_firmware( enum fw_type type )
+{
+#if defined(CONFIG_M4_LOAD_DDR_TRAINING)
+	uint32_t status;
+
+	printf("Set A53 ready\n");
+	writel(CMD_READY, TCMU_CMD_A53);
+
+	printf("Wait for M4 cmd finished\n");
+	status = readl(TCMU_ST_M4);
+	while(status != ST_FAIL && status != ST_SUCCESS)
+	{
+		status = readl(TCMU_ST_M4);
+		/*if(status == ST_EXCEPT)
+		{
+			printf( "M4 Exception : %d\n", readl(TCMU_CMD_M4));
+			return;
+		}*/
+	}
+
+	printf("Clear A53 command\n");
+	writel(0, TCMU_CMD_A53);
+	while(status != ST_READY)
+		status = readl(TCMU_ST_M4);
+	printf("Cortex M4 synchronized\n");
+
+	load_train_code_tcmu(type);
+	writel(type, TCMU_ARG_A53);
+	writel(0, TCMU_ST_A53);
+	printf("Cmd write firmware\n");
+	writel(CMD_WRITE_FW, TCMU_CMD_A53);
+
+	status = readl(TCMU_ST_M4);
+	printf("Wait for M4 to complete\n");
+	while(status != ST_FAIL && status != ST_SUCCESS)
+	{
+		status = readl(TCMU_ST_M4);
+		/*if(status == ST_EXCEPT)
+		{
+			printf( "M4 Exception : %d\n", readl(TCMU_CMD_M4));
+			return;
+		}*/
+	}
+
+	/*
+	printf("ddr trainging code loaded - type 0x%x\n", type);