Commit a45f33aa authored by Eric Kuzmenko's avatar Eric Kuzmenko
Browse files

Configure the SDA and SCL pins of each I2C bus to have a drive strength of...

Configure the SDA and SCL pins of each I2C bus to have a drive strength of 45Ohms, a slew rate of 50MHz, and disable their internal pull-up resistors
parent 2270b6cd
...@@ -86,29 +86,29 @@ ...@@ -86,29 +86,29 @@
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
fsl,pins = < fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000003f MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000003f MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026
>; >;
}; };
pinctrl_i2c2: i2c2grp { pinctrl_i2c2: i2c2grp {
fsl,pins = < fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026
>; >;
}; };
pinctrl_i2c3: i2c3grp { pinctrl_i2c3: i2c3grp {
fsl,pins = < fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026
>; >;
}; };
pinctrl_i2c4: i2c4grp { pinctrl_i2c4: i2c4grp {
fsl,pins = < fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000003f MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000003f MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026
>; >;
}; };
......
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