Commit ab2f9e13 authored by Peng Fan's avatar Peng Fan Committed by Ye Li
Browse files

MLK-14418-8 imx: mx7dsabresd: add epdc support



Add epdc support from v2016.03.
Add a epdc specified DTS file for using epdc
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
parent 0137915e
......@@ -363,6 +363,7 @@ dtb-$(CONFIG_MX6) += imx6ul-14x14-ddr3-arm2.dtb \
dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
imx7d-sdb.dtb \
imx7d-sdb-epdc.dtb \
imx7d-sdb-reva.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
......
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-epdc.dtsi"
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&epdc {
status = "okay";
};
&fec1 {
status = "disabled";
};
&fec2 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&max17135 {
status = "okay";
};
&sii902x {
status = "disabled";
};
&sim1 {
status = "disabled";
};
&uart5 {
status = "disabled";
};
&i2c3 {
elan@10 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_elan_touch>;
compatible = "elan,elan-touch";
reg = <0x10>;
interrupt-parent = <&gpio6>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
gpio_elan_cs = <&gpio6 13 0>;
gpio_elan_rst = <&gpio6 15 0>;
gpio_intr = <&gpio6 12 0>;
status = "okay";
};
};
......@@ -22,6 +22,10 @@
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <asm/arch/crm_regs.h>
#if defined(CONFIG_MXC_EPDC)
#include <lcd.h>
#include <mxc_epdc_fb.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
......@@ -43,6 +47,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#define EPDC_PAD_CTRL 0x0
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
......@@ -306,6 +312,221 @@ int board_qspi_init(void)
}
#endif
#ifdef CONFIG_MXC_EPDC
iomux_v3_cfg_t const epdc_en_pads[] = {
MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const epdc_enable_pads[] = {
MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
};
static iomux_v3_cfg_t const epdc_disable_pads[] = {
MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
};
vidinfo_t panel_info = {
.vl_refresh = 85,
.vl_col = 1024,
.vl_row = 758,
.vl_pixclock = 40000000,
.vl_left_margin = 12,
.vl_right_margin = 76,
.vl_upper_margin = 4,
.vl_lower_margin = 5,
.vl_hsync = 12,
.vl_vsync = 2,
.vl_sync = 0,
.vl_mode = 0,
.vl_flag = 0,
.vl_bpix = 3,
.cmap = 0,
};
struct epdc_timing_params panel_timings = {
.vscan_holdoff = 4,
.sdoed_width = 10,
.sdoed_delay = 20,
.sdoez_width = 10,
.sdoez_delay = 20,
.gdclk_hp_offs = 524,
.gdsp_offs = 327,
.gdoe_offs = 0,
.gdclk_offs = 19,
.num_ce = 1,
};
static void setup_epdc_power(void)
{
/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
/* Setup epdc voltage */
/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat");
gpio_direction_input(IMX_GPIO_NR(2, 31));
/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom");
gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_request(IMX_GPIO_NR(2, 23), "epdc_pmic");
gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_request(IMX_GPIO_NR(2, 30), "epdc_pwr_ctl0");
gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
}
static void epdc_enable_pins(void)
{
/* epdc iomux settings */
imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
ARRAY_SIZE(epdc_enable_pads));
}
static void epdc_disable_pins(void)
{
/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
ARRAY_SIZE(epdc_disable_pads));
}
static void setup_epdc(void)
{
/*** epdc Maxim PMIC settings ***/
/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set pixel clock rates for EPDC in clock.c */
panel_info.epdc_data.wv_modes.mode_init = 0;
panel_info.epdc_data.wv_modes.mode_du = 1;
panel_info.epdc_data.wv_modes.mode_gc4 = 3;
panel_info.epdc_data.wv_modes.mode_gc8 = 2;
panel_info.epdc_data.wv_modes.mode_gc16 = 2;
panel_info.epdc_data.wv_modes.mode_gc32 = 2;
panel_info.epdc_data.epdc_timings = panel_timings;
setup_epdc_power();
}
void epdc_power_on(void)
{
unsigned int reg;
struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
gpio_set_value(IMX_GPIO_NR(2, 30), 1);
udelay(1000);
/* Enable epdc signal pin */
epdc_enable_pins();
/* Set PMIC Wakeup to high - enable Display power */
gpio_set_value(IMX_GPIO_NR(2, 23), 1);
/* Wait for PWRGOOD == 1 */
while (1) {
reg = readl(&gpio_regs->gpio_psr);
if (!(reg & (1 << 31)))
break;
udelay(100);
}
/* Enable VCOM */
gpio_set_value(IMX_GPIO_NR(4, 14), 1);
udelay(500);
}
void epdc_power_off(void)
{
/* Set PMIC Wakeup to low - disable Display power */
gpio_set_value(IMX_GPIO_NR(2, 23), 0);
/* Disable VCOM */
gpio_set_value(IMX_GPIO_NR(4, 14), 0);
epdc_disable_pins();
/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
gpio_set_value(IMX_GPIO_NR(2, 30), 0);
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
......@@ -334,6 +555,20 @@ int board_init(void)
board_qspi_init();
#endif
#ifdef CONFIG_MXC_EPDC
if (mx7sabre_rev() >= BOARD_REV_B) {
/*
* On RevB, GPIO1_IO04 is used for ENET2 EN,
* so set its output to high to isolate the
* ENET2 signals for EPDC
*/
imx_iomux_v3_setup_multiple_pads(epdc_en_pads,
ARRAY_SIZE(epdc_en_pads));
gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
}
setup_epdc();
#endif
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
......
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-epdc"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_MXC_EPDC=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SPI=y
CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_ERRNO_STR=y
......@@ -20,6 +20,7 @@
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Network */
#ifdef CONFIG_DM_ETH
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RGMII
......@@ -39,6 +40,7 @@
#endif
#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
#endif
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
......@@ -289,6 +291,31 @@
#define CONFIG_IMX_VIDEO_SKIP
#endif
/* #define CONFIG_SPLASH_SCREEN*/
/* #define CONFIG_MXC_EPDC*/
/*
* SPLASH SCREEN Configs
*/
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
/*
* Framebuffer and LCD
*/
#define CONFIG_CMD_BMP
#define CONFIG_LCD
#undef LCD_TEST_PATTERN
/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
#define LCD_BPP LCD_MONOCHROME
/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
#endif
#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_SYS_USE_QSPI)
#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
#endif
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_MACRONIX
......
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