Skip to content

GitLab

Commit b6122733 authored by Peng Fan's avatar Peng Fan Committed by Ye Li
Browse files

MLK-14419-1 imx: mx7d_arm2: add 12x12 lpddr3 arm2 support 



Add mx7d 12x12 lpddr3 arm2 support, which has enabled the OF_CONTROL
and DM drivers
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
parent 32147576
Expand all Hide whitespace changes
Inline Side-by-side
arch/arm/cpu/armv7/mx7/Kconfig
View file @ b6122733
......@@ -23,6 +23,13 @@ config TARGET_MX7DSABRESD
select DM
select DM_THERMAL
config TARGET_MX7D_12X12_LPDDR3_ARM2
bool "Support mx7d_12x12_lpddr3_arm2"
select BOARD_LATE_INIT
select MX7D
select DM
select DM_THERMAL
config TARGET_WARP7
bool "warp7"
select BOARD_LATE_INIT
......@@ -43,6 +50,7 @@ config SYS_SOC
default "mx7"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"
......
arch/arm/dts/Makefile
View file @ b6122733
......@@ -366,7 +366,10 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
imx7d-sdb-epdc.dtb \
imx7d-sdb-gpmi-weim.dtb \
imx7d-sdb-qspi.dtb \
imx7d-sdb-reva.dtb
imx7d-sdb-reva.dtb \
imx7d-12x12-lpddr3-arm2.dtb \
imx7d-12x12-lpddr3-arm2-ecspi.dtb \
imx7d-12x12-lpddr3-arm2-qspi.dtb \
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
......
arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts 0 → 100644
View file @ b6122733
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-12x12-lpddr3-arm2.dts"
&epdc {
status = "disabled";
};
&ecspi1{
status = "okay";
};
/*
* pin conflict with ecspi1
* default hog setting conflicts with ECSPI1 MOSI and MISO
* EPDC PWRCTRL conflicts with ECSPI1 CS pin
*/
&iomuxc {
pinctrl-0 = <&pinctrl_hog_1>;
pinctrl-1 = <&pinctrl_hog_1>;
};
arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts 0 → 100644
View file @ b6122733
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-12x12-lpddr3-arm2.dts"
/* disable epdc, conflict with qspi */
&epdc {
status = "disabled";
};
&iomuxc {
qspi1 {
pinctrl_qspi1_1: qspi1grp_1 {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51
MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51
MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51
MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51
MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51
MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51
MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51
MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51
MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51
>;
};
};
};
&qspi1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_qspi1_1>;
pinctrl-1 = <&pinctrl_qspi1_1>;
status = "okay";
fsl,qspi-has-second-chip = <1>;
ddrsmp=<0>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <0>;
};
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <1>;
};
flash2: n25q256a@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <2>;
};
flash3: n25q256a@3 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <3>;
};
};
arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts 0 → 100644
View file @ b6122733
This diff is collapsed.
board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig 0 → 100644
View file @ b6122733
if TARGET_MX7D_12X12_LPDDR3_ARM2
config SYS_BOARD
default "mx7d_12x12_lpddr3_arm2"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx7"
config SYS_CONFIG_NAME
default "mx7d_12x12_lpddr3_arm2"
endif
board/freescale/mx7d_12x12_lpddr3_arm2/Makefile 0 → 100644
View file @ b6122733
# (C) Copyright 2015 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx7d_12x12_lpddr3_arm2.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg 0 → 100644
View file @ b6122733
/*
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
BOOT_FROM sd
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x30340004 0x4F400005
/* Clear then set bit30 to ensure exit from DDR retention */
DATA 4 0x30360388 0x40000000
DATA 4 0x30360384 0x40000000
DATA 4 0x30391000 0x00000002
DATA 4 0x307a0000 0x03040008
DATA 4 0x307a0064 0x00200038
DATA 4 0x307a0490 0x00000001
DATA 4 0x307a00d0 0x00350001
DATA 4 0x307a00dc 0x00c3000a
DATA 4 0x307a00e0 0x00010000
DATA 4 0x307a00e4 0x00110006
DATA 4 0x307a00f4 0x0000033f
DATA 4 0x307a0100 0x0a0e110b
DATA 4 0x307a0104 0x00020211
DATA 4 0x307a0108 0x03060708
DATA 4 0x307a010c 0x00a0500c
DATA 4 0x307a0110 0x05020307
DATA 4 0x307a0114 0x02020404
DATA 4 0x307a0118 0x02020003
DATA 4 0x307a011c 0x00000202
DATA 4 0x307a0120 0x00000202
DATA 4 0x307a0180 0x00600018
DATA 4 0x307a0184 0x00e00100
DATA 4 0x307a0190 0x02098205
DATA 4 0x307a0194 0x00060303
DATA 4 0x307a01a0 0x80400003
DATA 4 0x307a01a4 0x00100020
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0200 0x00000016
DATA 4 0x307a0204 0x00171717
DATA 4 0x307a0210 0x00000f00
DATA 4 0x307a0214 0x05050505
DATA 4 0x307a0218 0x0f0f0505
DATA 4 0x307a0240 0x06000601
DATA 4 0x307a0244 0x00000000
DATA 4 0x30391000 0x00000000
DATA 4 0x30790000 0x17421e40
DATA 4 0x30790004 0x10210100
DATA 4 0x30790008 0x00010000
DATA 4 0x30790010 0x0007080c
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079001C 0x01010000
DATA 4 0x3079009c 0x0db60d6e
DATA 4 0x30790030 0x06060606
DATA 4 0x30790020 0x0a0a0a0a
DATA 4 0x30790050 0x01000008
DATA 4 0x30790050 0x00000008
DATA 4 0x30790018 0x0000000f
DATA 4 0x307900c0 0x1e487304
DATA 4 0x307900c0 0x1e487304
DATA 4 0x307900c0 0x1e487306
DATA 4 0x307900c0 0x1e4c7304
CHECK_BITS_SET 4 0x307900c4 0x1
DATA 4 0x307900c0 0x1e487304
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x30384130 0x00000002
CHECK_BITS_SET 4 0x307a0004 0x1
#endif
board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg 0 → 100644
View file @ b6122733
/*
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
BOOT_FROM sd
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x30340004 0x4F400005
/* Clear then set bit30 to ensure exit from DDR retention */
DATA 4 0x30360388 0x40000000
DATA 4 0x30360384 0x40000000
DATA 4 0x30391000 0x00000002
DATA 4 0x307a0000 0x03040008
DATA 4 0x307a0064 0x00200038
DATA 4 0x307a0490 0x00000001
DATA 4 0x307a00d0 0x00350001
DATA 4 0x307a00dc 0x00c3000a
DATA 4 0x307a00e0 0x00010000
DATA 4 0x307a00e4 0x00110006
DATA 4 0x307a00f4 0x0000033f
DATA 4 0x307a0100 0x0a0e110b
DATA 4 0x307a0104 0x00020211
DATA 4 0x307a0108 0x03060708
DATA 4 0x307a010c 0x00a0500c
DATA 4 0x307a0110 0x05020307
DATA 4 0x307a0114 0x02020404
DATA 4 0x307a0118 0x02020003
DATA 4 0x307a011c 0x00000202
DATA 4 0x307a0120 0x00000202
DATA 4 0x307a0180 0x00600018
DATA 4 0x307a0184 0x00e00100
DATA 4 0x307a0190 0x02098205
DATA 4 0x307a0194 0x00060303
DATA 4 0x307a01a0 0x80400003
DATA 4 0x307a01a4 0x00100020
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0200 0x00000016
DATA 4 0x307a0204 0x00171717
DATA 4 0x307a0210 0x00000f00
DATA 4 0x307a0214 0x05050505
DATA 4 0x307a0218 0x0f0f0505
DATA 4 0x307a0240 0x06000601
DATA 4 0x307a0244 0x00000000
DATA 4 0x30391000 0x00000000
DATA 4 0x30790000 0x17421e40
DATA 4 0x30790004 0x10210100
DATA 4 0x30790008 0x00010000
DATA 4 0x30790010 0x0007080c
DATA 4 0x3079007c 0x1c1c1c1c
DATA 4 0x30790080 0x1c1c1c1c
DATA 4 0x30790084 0x30301c1c
DATA 4 0x30790088 0x00000030
DATA 4 0x3079006c 0x30303030
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079001C 0x01010000
DATA 4 0x3079009c 0x0db60d6e
DATA 4 0x30790030 0x06060606
DATA 4 0x30790020 0x0a0a0a0a
DATA 4 0x30790050 0x01000008
DATA 4 0x30790050 0x00000008
DATA 4 0x30790018 0x0000000f
DATA 4 0x307900c0 0x1e487304
DATA 4 0x307900c0 0x1e487304
DATA 4 0x307900c0 0x1e487306
DATA 4 0x307900c0 0x1e4c7304
CHECK_BITS_SET 4 0x307900c4 0x1
DATA 4 0x307900c0 0x1e487304
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x30384130 0x00000002
CHECK_BITS_SET 4 0x307a0004 0x1
#endif
board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c 0 → 100644
View file @ b6122733
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <asm/arch/crm_regs.h>
#include <asm/imx-common/video.h>
#ifdef CONFIG_VIDEO_MXS
#include <linux/fb.h>
#endif
#if defined(CONFIG_MXC_EPDC)
#include <lcd.h>
#include <mxc_epdc_fb.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_DSE_3P3V_49OHM)
#define QSPI_PAD_CTRL \
(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define EPDC_PAD_CTRL 0x0
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
};
static iomux_v3_cfg_t const pwm_pads[] = {
/* Use GPIO for Brightness adjustment, duty cycle = period */
MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
void do_enable_parallel_lcd(struct display_info_t const *dev)
{
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
/* Power up the LCD */
gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
/* Set Brightness to high */
gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
}
struct display_info_t const displays[] = {{
.bus = ELCDIF1_IPS_BASE_ADDR,
.addr = 0,
.pixfmt = 24,
.detect = NULL,
.enable = do_enable_parallel_lcd,
.mode = {
.name = "MCIMX28LCD",
.xres = 800,
.yres = 480,
.pixclock = 29850,
.left_margin = 89,
.right_margin = 164,
.upper_margin = 23,
.lower_margin = 10,
.hsync_len = 10,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
#endif
static iomux_v3_cfg_t const per_rst_pads[] = {
MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec1(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_QSPI
#ifndef CONFIG_DM_SPI
static iomux_v3_cfg_t const quadspi_pads[] = {
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),