Commit b934ca4f authored by Peng Fan's avatar Peng Fan Committed by Jason Liu
Browse files

MLK-15290 imx8mq: evk: add wdog reset support



Power down wdog counter to avoid reset after 16 seconds.
Add set_wdog_set to configure wcr to use WDOG_B reset.
Configure iomux to output WDOG_B to reset system.
Build watchdog driver for imx8mq.
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
parent 53837cba
......@@ -92,7 +92,7 @@ config PSCI_RESET
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB && \
!ARCH_IMX8
!ARCH_IMX8 && !ARCH_IMX8M
help
Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.
......
......@@ -580,6 +580,14 @@ int clock_init()
clock_enable(CCGR_USB_PHY1, 1);
clock_enable(CCGR_USB_PHY2, 1);
clock_enable(CCGR_WDOG1, 0);
clock_enable(CCGR_WDOG2, 0);
clock_enable(CCGR_WDOG3, 0);
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_WDOG1, 1);
clock_enable(CCGR_WDOG2, 1);
clock_enable(CCGR_WDOG3, 1);
return 0;
};
......
......@@ -39,12 +39,32 @@ int timer_init(void)
return 0;
}
void set_wdog_reset(struct wdog_regs *wdog)
{
u32 reg = readw(&wdog->wcr);
/*
* Output WDOG_B signal to reset external pmic or POR_B decided by
* the board desgin. Without external reset, the peripherals/DDR/
* PMIC are not reset, that may cause system working abnormal.
*/
reg = readw(&wdog->wcr);
reg |= 1 << 3;
/*
* WDZST bit is write-once only bit. Align this bit in kernel,
* otherwise kernel code will have no chance to set this bit.
*/
reg |= 1 << 0;
writew(reg, &wdog->wcr);
}
#ifdef CONFIG_SPL_BUILD
void reset_cpu(ulong addr)
{
/* TODO */
printf("%s\n", __func__);
while (1);
}
#endif
static struct mm_region imx8m_mem_map[] = {
{
......@@ -85,6 +105,18 @@ u32 get_cpu_rev(void)
return (MXC_CPU_IMX8MQ << 12) | (1 << 4);
}
void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
writew(enable, &wdog3->wmcr);
}
int arch_cpu_init(void)
{
/*
......@@ -94,6 +126,8 @@ int arch_cpu_init(void)
timer_init();
clock_init();
imx_set_wdog_powerdown(false);
return 0;
}
......
......@@ -233,6 +233,14 @@ struct src {
u32 ddr2_rcr;
};
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wrsr; /* Reset Status */
u16 wicr; /* Interrupt Control */
u16 wmcr; /* Miscellaneous Control */
};
#endif
#endif /* __ASM_ARCH_MSCALE_REGS_H__ */
......@@ -5,3 +5,5 @@
*/
#include <asm/imx-common/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog);
......@@ -16,6 +16,7 @@
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/clock.h>
......@@ -40,6 +41,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL_MII_MDC (PAD_CTL_DSE3 | PAD_CTL_FSEL0)
#define ENET_RX_PAD_CTRL (PAD_CTL_DSE7 | PAD_CTL_FSEL3)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#ifdef CONFIG_FSL_QSPI
static iomux_v3_cfg_t const qspi_pads[] = {
IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
......@@ -351,6 +358,18 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
return 0;
}
int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
return 0;
}
......
......@@ -7,7 +7,7 @@
obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610))
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 imx8m))
obj-y += imx_watchdog.o
endif
obj-$(CONFIG_S5P) += s5p_wdt.o
......
......@@ -42,6 +42,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_BOARD_LATE_INIT
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
......
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